rom.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 52 行

------------------------------------------------------------------------
--  rom_digits.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the rom_digits component
------------------------------------------------------------------------
--  Behavioral description
-- A memory with hex as addres and seven segment as output
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rom_digits is
	port( add: in std_logic_vector(3 downto 0); 
			digit : out std_logic_vector(6 downto 0)
	);
end rom_digits;

architecture Behavioral of rom_digits is

type memorie is array(0 to 15) of std_logic_vector(6 downto 0);
constant mem : memorie :=
	(  
	"0000001", -- 0  
	"1001111", -- 1  
	"0010010", -- 2
	"0000110", -- 3
	"1001100", -- 4
	"0100100", -- 4
	"0100000", -- 6
	"0001111", -- 7
	"0000000", -- 8
	"0000100", -- 9
	"0001000", -- A
	"1100000", -- B
	"0110001", -- C
	"1000010", -- D
	"0110000", -- E
	"0111000"	 -- F
	);
 
begin
	digit <= mem(conv_integer(add)); 

end Behavioral;