timer.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  timer.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the timer component
------------------------------------------------------------------------
--  Behavioral description
-- it is a counter that measures seconds 	seconds with the outputs
-- designed for the 7 segment display.	
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity timer is
	port( clk, reset, enable: in std_logic;
			d1,d2,d3,d4:out std_logic_vector (3 downto 0)
		 );
end timer;

architecture Behavioral of timer is

begin
	
	process (clk)
	variable 
		num:std_logic_vector(25 downto 0):="00000000000000000000000000";
-------------------------------------------------------------
--this is what will be displyed on the 7 segment display
-------------------------------------------------------------
	variable vd1:std_logic_vector (3 downto 0):="0000";
	variable vd2:std_logic_vector (3 downto 0):="0000";
	variable vd3:std_logic_vector (3 downto 0):="0000";
	variable vd4:std_logic_vector (3 downto 0):="0000";
	begin
		if (clk'event and clk='1') then
			if (reset='1') then
				vd1:="0000";vd2:="0000";vd3:="0000";vd4:="0000";
				num:="00000000000000000000000000";
			else
				if (enable='1') then
					num:=num+1;
					if (num="10111110101111000010000000") then
						num:="00000000000000000000000000";
						vd1:=vd1+1;
						if (vd1="1010") then
							vd2:=vd2+1;
							vd1:="0000";
						end if;
						if (vd2="1010") then
							vd3:=vd3+1;
							vd2:="0000";
						end if;
						if (vd3="1010") then
							vd4:=vd4+1;
							vd3:="0000";
						end if;
						if (vd4="1010") then
							vd4:="0000";
						end if;
					end if;
				end if;
			end if;
			d1<=vd1;d2<=vd2;d3<=vd3;d4<=vd4;
		end if;
	end process;

end Behavioral;