mux2_1_6bits.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 36 行

------------------------------------------------------------------------
--  mux2_1_6bits.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the mux2_1_6bits component
------------------------------------------------------------------------
--  Behavioral description
-- A 2:1 MUX witn 6 bits inputs and output
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2_1_6bits is
	port(a,b:in std_logic_vector (5 downto 0);
				s:in std_logic;
				c:out std_logic_vector (5 downto 0));
end mux2_1_6bits;

architecture Behavioral of mux2_1_6bits is

begin

	process (s,a,b)
	begin
		if (s='0') then c<=a;
		else c<=b;
		end if;
	end process;

end Behavioral;