mux8_1_3bits.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  mux8_1_3bits.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the mux8_1_3bits component
------------------------------------------------------------------------
--  Behavioral description
-- A 8:1 MUX witn 3 bits inputs and output
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux8_1_3bits is
	port(a,b,c,d,e,f,g,h:in std_logic_vector(2 downto 0);
			s:in std_logic_vector(2 downto 0);
			o:out std_logic_vector(2 downto 0)
	);
end mux8_1_3bits;

architecture Behavioral of mux8_1_3bits is

begin
	process (s)
	begin
		if s="000" then o<=a; end if;
		if s="001" then o<=b; end if;
		if s="010" then o<=c; end if;
		if s="011" then o<=d; end if;
		if s="100" then o<=e; end if;
		if s="101" then o<=f; end if;
		if s="110" then o<=g; end if;
		if s="111" then o<=h; end if;
	end process;

end Behavioral;