timer_enable.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 46 行

------------------------------------------------------------------------
--  timer_enable.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the timer_enable component
------------------------------------------------------------------------
--  Behavioral description
--  This is the enable for the timer
--  When the game has started, first	
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity timer_enable is
	port( done,RDY,reset: in std_logic;
			enable: out std_logic:='0'
		 );
end timer_enable;

architecture Behavioral of timer_enable is

begin

	process (done,RDY)
	begin
		if (reset='1') then
			enable<='0';
		else
			if (done='1') then
				enable<='0';
			else
				if (RDY='1') then
					enable<='1';
				end if;
			end if;
		end if;
	end process;

end Behavioral;