decod_2bits.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 38 行

------------------------------------------------------------------------
--  decod_2bits.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the decod_2bits component
------------------------------------------------------------------------
--  Behavioral description
-- A 2 bits decoder
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decod_2bits is
	port( i:in std_logic_vector (1 downto 0);
			o0,o1,o2,o3:out std_logic
		 );
end decod_2bits;

architecture Behavioral of decod_2bits is

begin

	process (i)
	begin
		if (i="00") then o0<='0'; o1<='1'; o2<='1'; o3<='1'; end if;
		if (i="01") then o0<='1'; o1<='0'; o2<='1'; o3<='1'; end if;
		if (i="10") then o0<='1'; o1<='1'; o2<='0'; o3<='1'; end if;
		if (i="11") then o0<='1'; o1<='1'; o2<='1'; o3<='0'; end if;
	end process;

end Behavioral;