validate_positions.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 55 行

------------------------------------------------------------------------
--  validate_positions.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the validate_positions component
------------------------------------------------------------------------
--  Behavioral description
-- Validates the new positions(the output of new_positions coponent), 
-- and if them are valid, the selection for the new positions 
--	is activated(s <='1')
-- A position is valid if the character is empty (000) or the door(010)
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity validate_positions is
	port(	clk,reset,new_c:in std_logic;
			char:in std_logic_vector (2 downto 0);
			done: out std_logic:='0';
			S:out std_logic);
end validate_positions;

architecture Behavioral of validate_positions is

begin

	process (clk)
	begin
		if (clk'event and clk='1') then
			if (reset='1') then
				done<='0';
			else
				if (new_c='1') then
					if (char="000") then 		 --empty
						S<='1';
					end if;
					if (char="010") then		 --door
						S<='1';
						done<='1';
					end if;
				else
					S<='0';
				end if;
			end if;
		end if;
	end process;

end Behavioral;