labirint.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  labirint.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This is the source file where the component's mapping is done
-- Each of the following components are treated separately
-- in their	source files
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity labirint is
	port( clock_50Mhz, reset, KD, KC : in std_logic;
			led1,led2,led3,led4,led5,led6,led7,led8 : out std_logic;
			ldg : out std_logic;
			red_out, green_out, blue_out: out std_logic;
			horiz_sync_out, vert_sync_out : out std_logic;
			an1,an2,an3,an4:out std_logic;
			ca,cb,cc,cd,ce,cf,cg:out std_logic
		);
end labirint;

architecture Behavioral of labirint is
component char_generator is
	port(char:in std_logic_vector(2 downto 0);
			pixel_row,pixel_col:in std_logic_vector(9 downto 0);
			posR,posC:in std_logic_vector(5 downto 0);
			RGB:out std_logic_vector(2 downto 0)
	);
end component char_generator;

component div16 is
	port(pixel_row,pixel_col:in std_logic_vector(9 downto 0);
			p_r,p_c:out std_logic_vector (5 downto 0)
	);
end component div16;

component rom_labirint is
	port(row, col : in std_logic_vector(5 downto 0); 
			char : out std_logic_vector(2 downto 0)
	);
end component rom_labirint;

component vga is
	port(clock_25Mhz, red, green, blue : in std_logic;
			red_out, green_out, blue_out : out std_logic; 
			horiz_sync_out, vert_sync_out : out std_logic;
			pixel_row, pixel_column : out std_logic_vector(9 downto 0));
end component vga;

component div_clk_25Mhz is
	port(clock_50Mhz:in std_logic;
			clk25:out std_logic);
end component div_clk_25Mhz;

component reg_6bits is
port(clk, reset, load : in std_logic; 
		a : in std_logic_vector(5 downto 0);
		y : out std_logic_vector(5 downto 0)
	);
end component reg_6bits;

component keyboard is
Port(CLK, KD, KC: in std_logic;
	  RDY: buffer std_logic;
	  scancode: out std_logic_vector (7 downto 0)
	  );
end component keyboard;

component new_positions is
	port(	clk:in std_logic;
			R,C:in std_logic_vector (5 downto 0);
			key:in std_logic_vector (7 downto 0);
			RDY:in std_logic;
			NR,NC:out std_logic_vector (5 downto 0);
			new_c:out std_logic);
end component new_positions;

component mux2_1_6bits is
	port(a,b:in std_logic_vector (5 downto 0);
				s:in std_logic;
				c:out std_logic_vector (5 downto 0));
end component mux2_1_6bits;

component validate_positions is
	port(	clk,reset,new_c:in std_logic;
			char:in std_logic_vector (2 downto 0);
			done: out std_logic:='0';
			S:out std_logic);
end component validate_positions;

component div_clk_6hz is
	port(clock_50Mhz:in std_logic;
			clk23b:out std_logic);
end component div_clk_6hz;

component light is
	port (clk,reset: in std_logic;
		done: in std_logic;
		led1,led2,led3,led4,led5,led6,led7,led8 : out std_logic);
end component light;

component seg7_display is
	port( d1,d2,d3,d4:in std_logic_vector (3 downto 0);
			clk:in std_logic;
			an1,an2,an3,an4:out std_logic;
			ca,cb,cc,cd,ce,cf,cg:out std_logic
		 );
end component seg7_display;

component timer is
	port( clk, reset, enable: in std_logic;
			d1,d2,d3,d4:out std_logic_vector (3 downto 0)
		 );
end component timer;

component timer_enable is
	port( done,RDY,reset: in std_logic;
			enable: out std_logic:='0'
		 );
end component timer_enable;

signal clk25 : std_logic:='0';
signal tenable,clk23b,done,RDY,Sout,new_c : std_logic;
signal p_r,p_c : std_logic_vector(9 downto 0);
signal RGB,char : std_logic_vector(2 downto 0);
signal div8Out_r,div8Out_c: std_logic_vector(5 downto 0); 
signal NposR,NposC,posR,posC: std_logic_vector(5 downto 0); 
signal mem_r,mem_c : std_logic_vector(5 downto 0); 
signal key : std_logic_vector(7 downto 0); 
signal d1_out,d2_out,d3_out,d4_out: std_logic_vector (3 downto 0);

begin
		ldg<='1';

		divClk_50 : div_clk_25Mhz 
			port map (clock_50Mhz=>clock_50Mhz, clk25=>clk25);

		v : vga port map (clock_25Mhz =>clk25, 
			red=> RGB(2), green=>RGB(1), blue=>RGB(0), 
			red_out=>red_out, green_out=>green_out, blue_out=>blue_out,
			horiz_sync_out=>horiz_sync_out,vert_sync_out=>vert_sync_out,
			pixel_row=>p_r, pixel_column=>p_c
		);

		div : div16 port map (pixel_row=>p_r, pixel_col=>p_c,
			p_r=>div8Out_r,p_c=>div8Out_c
		);

		muxR : mux2_1_6bits port map (a=>div8Out_r,b=>NposR,
			s=>new_c,c=>mem_r
		);
		muxC : mux2_1_6bits port map (a=>div8Out_c,b=>NposC,
			s=>new_c,c=>mem_c
		);

		mem : rom_labirint port map (row=>mem_r, col=>mem_c, 
			char=>char
		);

		Reg7bitsRow : reg_6bits port map (clk=>clock_50Mhz, 
			reset=>reset, load=>Sout, a=>NposR, y=>posR
		);
		Reg7bitsCol : reg_6bits port map (clk=>clock_50Mhz, 
			reset=>reset, load=>Sout, a=>NposC, y=>posC
		);

		generator: char_generator port map (char=>char, 
			pixel_row=>p_r, pixel_col=>p_c,
			posR=>posR, posC=>posC, RGB=>RGB
		);

		keyboar : keyboard port map (CLK=>clock_50Mhz, 
			KD=>KD, KC=>KC, RDY=>RDY, scancode=>key
		);

		new_pos : new_positions port map (clk=>clock_50Mhz, 
			R=>posR, C=>posC, key=>key, RDY=>RDY,
			new_c=>new_c, NR=>NposR, NC=>NposC 
		);

		validate_position : validate_positions 
			port map(clk=>clock_50Mhz, reset=>reset, 
				new_c=>new_c, char=>char, done=>done, S=>Sout
			);

		div23p : div_clk_6hz port map (clock_50Mhz=>clock_50Mhz, 
			clk23b=>clk23b
		);

		lights : light port map(clk=>clk23b, reset=>reset, done=>done,
			led1=>led1, led2=>led2, led3=>led3, led4=>led4, 
			led5=>led5, led6=>led6, led7=>led7, led8=>led8
		);

		display : seg7_display 
			port map (d1=>d4_out,d2=>d3_out,d3=>d2_out,d4=>d1_out,
				clk=>clock_50Mhz,an1=>an1,an2=>an2,an3=>an3,an4=>an4,
				ca=>ca,cb=>cb,cc=>cc,cd=>cd,ce=>ce,cf=>cf,cg=>cg
			);

		t : timer port map (clk=>clock_50Mhz,reset=>reset,
			enable=>tenable,d1=>d1_out,d2=>d2_out,d3=>d3_out,d4=>d4_out
		);

		te : timer_enable port map (done=>done,RDY=>RDY,reset=>reset,
			enable=>tenable
		);

end Behavioral;