mux4_1_4bits.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  mux4_1_4bits.vhd -- 
------------------------------------------------------------------------
--  Authors : Albert Zemba & Mihai Cucicea
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1i 
--                   WebPack
------------------------------------------------------------------------
-- This source file contains the mux4_1_4bits component
------------------------------------------------------------------------
--  Behavioral description
-- A 4:1 Mux with 4 bits inputs and output
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux4_1_4bits is
	port( i0,i1,i2,i3:in std_logic_vector (3 downto 0);
			s:in std_logic_vector (1 downto 0);
			o:out std_logic_vector (3 downto 0)
		 );
end mux4_1_4bits;

architecture Behavioral of mux4_1_4bits is

begin

	process (i0,i1,i2,i3,s)
	begin
		if (s="00") then o<=i0; end if;
		if (s="01") then o<=i1; end if;
		if (s="10") then o<=i2; end if;
		if (s="11") then o<=i3; end if;
	end process;

end Behavioral;