pn_generator.vhd

来自「利用vhdl语言编程实现的pn码产生.在quartus ii中通过」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PN_GENERATOR IS
  PORT (
        CLK  : IN  STD_LOGIC;
        EN   : IN  STD_LOGIC;
        CLR  : IN  STD_LOGIC;
        --DATA : IN  STD_LOGIC_VECTOR( 6 DOWNTO 0);
        PN   : OUT STD_LOGIC
        );
END PN_GENERATOR;

ARCHITECTURE RUN OF PN_GENERATOR IS
  SIGNAL REG:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
  PN<=REG(0);
  PROCESS(CLK,EN,CLR)
  BEGIN
    IF CLK'EVENT AND CLK='1' THEN
       IF CLR = '0' THEN
          REG <= "1000000";
       ELSIF EN = '1' THEN
          REG <= (REG(0) XOR REG(4))&REG(6 DOWNTO 1);
       END IF;
    END IF;
  END PROCESS;
END RUN;