pn_generator.tan.qmsg

利用vhdl语言编程实现的pn码产生.在quartus ii中通过

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register REG\[6\] register REG\[6\] 100.0 MHz 10.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 100.0 MHz between source register \"REG\[6\]\" and destination register \"REG\[6\]\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.500 ns + Longest register register " "Info: + Longest register to register delay is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG\[6\] 1 REG LC2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 5.500 ns REG\[6\] 2 REG LC2 2 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 5.500 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { REG[6] REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 58.18 % ) " "Info: Total cell delay = 3.200 ns ( 58.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 41.82 % ) " "Info: Total interconnect delay = 2.300 ns ( 41.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { REG[6] REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { REG[6] {} REG[6] {} } { 0.000ns 2.300ns } { 0.000ns 3.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.600 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns REG\[6\] 2 REG LC2 2 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { CLK REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 100.00 % ) " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.600 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns REG\[6\] 2 REG LC2 2 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { CLK REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 100.00 % ) " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { REG[6] REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { REG[6] {} REG[6] {} } { 0.000ns 2.300ns } { 0.000ns 3.200ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "REG\[6\] EN CLK 6.200 ns register " "Info: tsu for register \"REG\[6\]\" (data pin = \"EN\", clock pin = \"CLK\") is 6.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns + Longest pin register " "Info: + Longest pin to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns EN 1 PIN PIN_41 15 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_41; Fanout = 15; PIN Node = 'EN'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 6.900 ns REG\[6\] 2 REG LC2 2 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { EN REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 66.67 % ) " "Info: Total cell delay = 4.600 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 33.33 % ) " "Info: Total interconnect delay = 2.300 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { EN REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { EN {} EN~out {} REG[6] {} } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns REG\[6\] 2 REG LC2 2 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { CLK REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 100.00 % ) " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { EN REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { EN {} EN~out {} REG[6] {} } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK PN REG\[0\] 7.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"PN\" through register \"REG\[0\]\" is 7.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns REG\[0\] 2 REG LC1 4 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC1; Fanout = 4; REG Node = 'REG\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { CLK REG[0] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 100.00 % ) " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register pin " "Info: + Longest register to pin delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG\[0\] 1 REG LC1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'REG\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG[0] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns PN 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'PN'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { REG[0] PN } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns ( 100.00 % ) " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { REG[0] PN } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.800 ns" { REG[0] {} PN {} } { 0.000ns 0.000ns } { 0.000ns 1.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { REG[0] PN } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.800 ns" { REG[0] {} PN {} } { 0.000ns 0.000ns } { 0.000ns 1.800ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "REG\[6\] EN CLK -2.000 ns register " "Info: th for register \"REG\[6\]\" (data pin = \"EN\", clock pin = \"CLK\") is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns REG\[6\] 2 REG LC2 2 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { CLK REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 100.00 % ) " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns EN 1 PIN PIN_41 15 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_41; Fanout = 15; PIN Node = 'EN'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 6.900 ns REG\[6\] 2 REG LC2 2 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG\[6\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { EN REG[6] } "NODE_NAME" } } { "PN_GENERATOR.vhd" "" { Text "D:/Study/EDA/FPGA_Project/PN/PN_GENERATOR.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 66.67 % ) " "Info: Total cell delay = 4.600 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 33.33 % ) " "Info: Total interconnect delay = 2.300 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { EN REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { EN {} EN~out {} REG[6] {} } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { CLK {} CLK~out {} REG[6] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { EN REG[6] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { EN {} EN~out {} REG[6] {} } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 04 21:49:36 2008 " "Info: Processing ended: Sun May 04 21:49:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}