pn_generator.tan.rpt

利用vhdl语言编程实现的pn码产生.在quartus ii中通过

; N/A   ; None         ; 6.200 ns   ; EN   ; REG[6] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; EN   ; REG[0] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; EN   ; REG[1] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; EN   ; REG[2] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; EN   ; REG[3] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; EN   ; REG[4] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; EN   ; REG[5] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; CLR  ; REG[6] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; CLR  ; REG[0] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; CLR  ; REG[1] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; CLR  ; REG[2] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; CLR  ; REG[3] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; CLR  ; REG[4] ; CLK      ;
; N/A   ; None         ; 6.200 ns   ; CLR  ; REG[5] ; CLK      ;
+-------+--------------+------------+------+--------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 7.000 ns   ; REG[0] ; PN ; CLK        ;
+-------+--------------+------------+--------+----+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -2.000 ns ; EN   ; REG[6] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; EN   ; REG[0] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; EN   ; REG[1] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; EN   ; REG[2] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; EN   ; REG[3] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; EN   ; REG[4] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; EN   ; REG[5] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; CLR  ; REG[6] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; CLR  ; REG[0] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; CLR  ; REG[1] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; CLR  ; REG[2] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; CLR  ; REG[3] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; CLR  ; REG[4] ; CLK      ;
; N/A           ; None        ; -2.000 ns ; CLR  ; REG[5] ; CLK      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Sun May 04 21:49:34 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PN_GENERATOR -c PN_GENERATOR
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 100.0 MHz between source register "REG[6]" and destination register "REG[6]" (period= 10.0 ns)
    Info: + Longest register to register delay is 5.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
        Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 5.500 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
        Info: Total cell delay = 3.200 ns ( 58.18 % )
        Info: Total interconnect delay = 2.300 ns ( 41.82 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.600 ns
            Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
            Info: Total cell delay = 3.600 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.600 ns
            Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
            Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "REG[6]" (data pin = "EN", clock pin = "CLK") is 6.200 ns
    Info: + Longest pin to register delay is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_41; Fanout = 15; PIN Node = 'EN'
        Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
        Info: Total cell delay = 4.600 ns ( 66.67 % )
        Info: Total interconnect delay = 2.300 ns ( 33.33 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
Info: tco from clock "CLK" to destination pin "PN" through register "REG[0]" is 7.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC1; Fanout = 4; REG Node = 'REG[0]'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'REG[0]'
        Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'PN'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
Info: th for register "REG[6]" (data pin = "EN", clock pin = "CLK") is -2.000 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_41; Fanout = 15; PIN Node = 'EN'
        Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC2; Fanout = 2; REG Node = 'REG[6]'
        Info: Total cell delay = 4.600 ns ( 66.67 % )
        Info: Total interconnect delay = 2.300 ns ( 33.33 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Sun May 04 21:49:36 2008
    Info: Elapsed time: 00:00:02