📄 frq.rpt
字号:
- 6 - B 09 OR2 ! 0 4 0 1 |DISPLAY_8_LED:4|:912
- 2 - B 04 OR2 0 4 1 0 |DISPLAY_8_LED:4|:1048
- 4 - B 10 OR2 0 4 1 0 |DISPLAY_8_LED:4|:1097
- 5 - B 09 OR2 s 0 4 0 1 |DISPLAY_8_LED:4|~1118~1
- 8 - B 09 OR2 0 3 0 1 |DISPLAY_8_LED:4|:1126
- 1 - B 09 OR2 0 4 0 1 |DISPLAY_8_LED:4|:1130
- 8 - B 07 AND2 0 4 0 1 |DISPLAY_8_LED:4|:1144
- 6 - B 07 OR2 0 4 1 0 |DISPLAY_8_LED:4|:1148
- 7 - B 09 OR2 0 4 0 1 |DISPLAY_8_LED:4|:1166
- 6 - B 04 OR2 0 4 1 0 |DISPLAY_8_LED:4|:1199
- 4 - B 04 OR2 0 4 1 0 |DISPLAY_8_LED:4|:1250
- 8 - B 04 OR2 0 4 1 0 |DISPLAY_8_LED:4|:1301
- 7 - B 10 OR2 0 4 1 0 |DISPLAY_8_LED:4|:1352
- 3 - B 21 DFFE 0 2 0 1 |REG32B:5|:34
- 3 - B 22 DFFE 0 2 0 1 |REG32B:5|:36
- 2 - B 19 DFFE 0 2 0 1 |REG32B:5|:38
- 2 - B 16 DFFE 0 2 0 1 |REG32B:5|:40
- 1 - B 21 DFFE 0 2 0 1 |REG32B:5|:42
- 2 - B 22 DFFE 0 2 0 1 |REG32B:5|:44
- 4 - B 23 DFFE 0 2 0 1 |REG32B:5|:46
- 1 - B 16 DFFE 0 2 0 1 |REG32B:5|:48
- 1 - B 15 DFFE 0 2 0 1 |REG32B:5|:50
- 6 - B 22 DFFE 0 2 0 1 |REG32B:5|:52
- 3 - C 23 DFFE 0 2 0 1 |REG32B:5|:54
- 6 - B 16 DFFE 0 2 0 1 |REG32B:5|:56
- 7 - B 21 DFFE 0 2 0 1 |REG32B:5|:58
- 8 - B 22 DFFE 0 2 0 1 |REG32B:5|:60
- 5 - C 23 DFFE 0 2 0 1 |REG32B:5|:62
- 8 - B 16 DFFE 0 2 0 1 |REG32B:5|:64
- 2 - C 20 DFFE 0 2 0 1 |REG32B:5|:66
- 2 - C 15 DFFE 0 2 0 1 |REG32B:5|:68
- 2 - C 18 DFFE 0 2 0 1 |REG32B:5|:70
- 2 - C 22 DFFE 0 2 0 1 |REG32B:5|:72
- 4 - C 20 DFFE 0 2 0 1 |REG32B:5|:74
- 4 - C 15 DFFE 0 2 0 1 |REG32B:5|:76
- 4 - C 18 DFFE 0 2 0 1 |REG32B:5|:78
- 4 - C 22 DFFE 0 2 0 1 |REG32B:5|:80
- 6 - C 20 DFFE 0 2 0 1 |REG32B:5|:82
- 6 - C 15 DFFE 0 2 0 1 |REG32B:5|:84
- 6 - C 18 DFFE 0 2 0 1 |REG32B:5|:86
- 6 - C 22 DFFE 0 2 0 1 |REG32B:5|:88
- 8 - C 20 DFFE 0 2 0 1 |REG32B:5|:90
- 8 - C 15 DFFE 0 2 0 1 |REG32B:5|:92
- 8 - C 18 DFFE 0 2 0 1 |REG32B:5|:94
- 8 - C 22 DFFE 0 2 0 1 |REG32B:5|:96
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\我的文档\zyl\37\s6\frq.rpt
frq
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 11/ 96( 11%) 5/ 48( 10%) 21/ 48( 43%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 16/ 96( 16%) 4/ 48( 8%) 30/ 48( 62%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 2/ 96( 2%) 0/ 48( 0%) 3/ 48( 6%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\我的文档\zyl\37\s6\frq.rpt
frq
** CLOCK SIGNALS **
Type Fan-out Name
DFF 67 |CONTROL:2|div2clk
INPUT 13 disclk
LCELL 7 |COUNT10:3|cnt10:U3|:173
LCELL 7 |COUNT10:3|cnt10:U0|:173
LCELL 7 |COUNT10:3|cnt10:U1|:173
LCELL 7 |COUNT10:3|cnt10:U2|:173
LCELL 7 |COUNT10:3|cnt10:U4|:173
LCELL 7 |COUNT10:3|cnt10:U5|:173
LCELL 7 |COUNT10:3|cnt10:U6|:173
INPUT 4 fsn
INPUT 2 clk
Device-Specific Information: d:\我的文档\zyl\37\s6\frq.rpt
frq
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 32 |CONTROL:2|:49
INPUT 2 reset
Device-Specific Information: d:\我的文档\zyl\37\s6\frq.rpt
frq
** EQUATIONS **
clk : INPUT;
disclk : INPUT;
fsn : INPUT;
reset : INPUT;
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = _LC7_B10;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC8_B4;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = _LC4_B4;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC6_B4;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC6_B7;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC4_B10;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = _LC2_B4;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC4_C14;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC8_C14;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC6_C14;
-- Node name is '|CONTROL:2|:6' = '|CONTROL:2|div2clk'
-- Equation name is '_LC1_D16', type is buried
_LC1_D16 = DFFE(!_LC1_D16, clk, !reset, VCC, VCC);
-- Node name is '|CONTROL:2|:49'
-- Equation name is '_LC2_D16', type is buried
!_LC2_D16 = _LC2_D16~NOT;
_LC2_D16~NOT = LCELL( _EQ001);
_EQ001 = _LC1_D16 & !reset
# clk & !reset;
-- Node name is '|COUNT10:3|cnt10:U0|:12' = '|COUNT10:3|cnt10:U0|cq10'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = DFFE( _EQ002, fsn, !_LC2_D16, VCC, VCC);
_EQ002 = _LC1_D16 & !_LC4_C13
# !_LC1_D16 & _LC4_C13;
-- Node name is '|COUNT10:3|cnt10:U0|:11' = '|COUNT10:3|cnt10:U0|cq11'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = DFFE( _EQ003, fsn, !_LC2_D16, VCC, VCC);
_EQ003 = _LC2_C13 & !_LC4_C13 & !_LC6_C13
# _LC1_D16 & !_LC2_C13 & _LC4_C13 & !_LC6_C13
# !_LC1_D16 & _LC2_C13;
-- Node name is '|COUNT10:3|cnt10:U0|:10' = '|COUNT10:3|cnt10:U0|cq12'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = DFFE( _EQ004, fsn, !_LC2_D16, VCC, VCC);
_EQ004 = !_LC6_C13 & !_LC7_C13 & _LC8_C13
# _LC1_D16 & !_LC6_C13 & _LC7_C13 & !_LC8_C13
# !_LC1_D16 & _LC8_C13;
-- Node name is '|COUNT10:3|cnt10:U0|:9' = '|COUNT10:3|cnt10:U0|cq13'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = DFFE( _EQ005, fsn, !_LC2_D16, VCC, VCC);
_EQ005 = _LC3_C13 & !_LC5_C13 & !_LC6_C13
# _LC1_D16 & !_LC3_C13 & _LC5_C13 & !_LC6_C13
# !_LC1_D16 & _LC3_C13;
-- Node name is '|COUNT10:3|cnt10:U0|LPM_ADD_SUB:73|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = LCELL( _EQ006);
_EQ006 = _LC2_C13 & _LC4_C13;
-- Node name is '|COUNT10:3|cnt10:U0|LPM_ADD_SUB:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = LCELL( _EQ007);
_EQ007 = _LC2_C13 & _LC4_C13 & _LC8_C13;
-- Node name is '|COUNT10:3|cnt10:U0|:173'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ008);
_EQ008 = !_LC2_C13 & _LC3_C13 & _LC4_C13 & !_LC8_C13;
-- Node name is '|COUNT10:3|cnt10:U1|:12' = '|COUNT10:3|cnt10:U1|cq10'
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = DFFE( _EQ009, _LC6_C13, !_LC2_D16, VCC, VCC);
_EQ009 = !_LC1_D16 & _LC6_C24
# _LC1_D16 & !_LC6_C24;
-- Node name is '|COUNT10:3|cnt10:U1|:11' = '|COUNT10:3|cnt10:U1|cq11'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = DFFE( _EQ010, _LC6_C13, !_LC2_D16, VCC, VCC);
_EQ010 = !_LC3_C24 & _LC4_C24 & !_LC6_C24
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