📄 frq.rpt
字号:
B15 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
B16 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 10/22( 45%)
B19 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
B21 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 10/22( 45%)
B22 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 10/22( 45%)
B23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 3/22( 13%)
C9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
C13 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 4/22( 18%)
C14 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
C15 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
C16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 5/22( 22%)
C17 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 7/22( 31%)
C18 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
C19 8/ 8(100%) 5/ 8( 62%) 7/ 8( 87%) 0/2 0/2 3/22( 13%)
C20 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
C21 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 2/2 1/2 7/22( 31%)
C22 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
C23 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 3/22( 13%)
D16 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 14/96 ( 14%)
Total logic cells used: 164/1152 ( 14%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.78/4 ( 69%)
Total fan-in: 457/4608 ( 9%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 10
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 164
Total flipflops required: 78
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 3/1152 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 4 0 0 8 0 8 2 0 0 0 8 0 8 8 0 0 3 0 7 8 8 0 72/0
C: 0 0 0 0 0 0 0 0 8 0 0 0 0 8 3 8 1 8 8 8 8 8 8 6 8 90/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 2/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 4 0 0 8 0 16 2 0 0 0 16 3 16 11 8 8 11 8 15 16 14 8 164/0
Device-Specific Information: d:\我的文档\zyl\37\s6\frq.rpt
frq
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
23 - - D -- INPUT 0 0 0 2 clk
26 - - E -- INPUT 0 0 0 13 disclk
27 - - E -- INPUT 0 0 0 4 fsn
7 - - A -- INPUT 0 0 0 2 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\我的文档\zyl\37\s6\frq.rpt
frq
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
90 - - C -- OUTPUT 0 1 0 0 led0
91 - - C -- OUTPUT 0 1 0 0 led1
92 - - C -- OUTPUT 0 1 0 0 led2
95 - - B -- OUTPUT 0 1 0 0 led3
96 - - B -- OUTPUT 0 1 0 0 led4
97 - - B -- OUTPUT 0 1 0 0 led5
98 - - B -- OUTPUT 0 1 0 0 led6
20 - - D -- OUTPUT 0 1 0 0 sel0
21 - - D -- OUTPUT 0 1 0 0 sel1
22 - - D -- OUTPUT 0 1 0 0 sel2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\我的文档\zyl\37\s6\frq.rpt
frq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - D 16 DFFE 2 0 0 66 |CONTROL:2|div2clk (|CONTROL:2|:6)
- 2 - D 16 OR2 ! 2 1 0 32 |CONTROL:2|:49
- 7 - C 13 AND2 0 2 0 1 |COUNT10:3|cnt10:U0|LPM_ADD_SUB:73|addcore:adder|:55
- 5 - C 13 AND2 0 3 0 1 |COUNT10:3|cnt10:U0|LPM_ADD_SUB:73|addcore:adder|:59
- 3 - C 13 DFFE 1 4 0 2 |COUNT10:3|cnt10:U0|cq13 (|COUNT10:3|cnt10:U0|:9)
- 8 - C 13 DFFE 1 4 0 3 |COUNT10:3|cnt10:U0|cq12 (|COUNT10:3|cnt10:U0|:10)
- 2 - C 13 DFFE 1 4 0 4 |COUNT10:3|cnt10:U0|cq11 (|COUNT10:3|cnt10:U0|:11)
- 4 - C 13 DFFE 1 2 0 5 |COUNT10:3|cnt10:U0|cq10 (|COUNT10:3|cnt10:U0|:12)
- 6 - C 13 AND2 0 4 0 7 |COUNT10:3|cnt10:U0|:173
- 8 - C 24 AND2 0 2 0 1 |COUNT10:3|cnt10:U1|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - C 24 AND2 0 3 0 1 |COUNT10:3|cnt10:U1|LPM_ADD_SUB:73|addcore:adder|:59
- 2 - C 24 DFFE 0 5 0 2 |COUNT10:3|cnt10:U1|cq13 (|COUNT10:3|cnt10:U1|:9)
- 5 - C 24 DFFE 0 5 0 3 |COUNT10:3|cnt10:U1|cq12 (|COUNT10:3|cnt10:U1|:10)
- 4 - C 24 DFFE 0 5 0 4 |COUNT10:3|cnt10:U1|cq11 (|COUNT10:3|cnt10:U1|:11)
- 6 - C 24 DFFE 0 3 0 5 |COUNT10:3|cnt10:U1|cq10 (|COUNT10:3|cnt10:U1|:12)
- 3 - C 24 AND2 0 4 0 7 |COUNT10:3|cnt10:U1|:173
- 8 - C 17 AND2 0 2 0 1 |COUNT10:3|cnt10:U2|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - C 17 AND2 0 3 0 1 |COUNT10:3|cnt10:U2|LPM_ADD_SUB:73|addcore:adder|:59
- 3 - C 17 DFFE 0 5 0 2 |COUNT10:3|cnt10:U2|cq13 (|COUNT10:3|cnt10:U2|:9)
- 5 - C 17 DFFE 0 5 0 3 |COUNT10:3|cnt10:U2|cq12 (|COUNT10:3|cnt10:U2|:10)
- 2 - C 17 DFFE 0 5 0 4 |COUNT10:3|cnt10:U2|cq11 (|COUNT10:3|cnt10:U2|:11)
- 1 - C 24 DFFE 0 3 0 5 |COUNT10:3|cnt10:U2|cq10 (|COUNT10:3|cnt10:U2|:12)
- 4 - C 17 AND2 0 4 0 7 |COUNT10:3|cnt10:U2|:173
- 6 - C 17 AND2 0 2 0 1 |COUNT10:3|cnt10:U3|LPM_ADD_SUB:73|addcore:adder|:55
- 5 - C 21 AND2 0 3 0 1 |COUNT10:3|cnt10:U3|LPM_ADD_SUB:73|addcore:adder|:59
- 8 - C 21 DFFE 0 5 0 2 |COUNT10:3|cnt10:U3|cq13 (|COUNT10:3|cnt10:U3|:9)
- 1 - C 17 DFFE 0 5 0 3 |COUNT10:3|cnt10:U3|cq12 (|COUNT10:3|cnt10:U3|:10)
- 4 - C 16 DFFE 0 5 0 4 |COUNT10:3|cnt10:U3|cq11 (|COUNT10:3|cnt10:U3|:11)
- 1 - C 13 DFFE 0 3 0 5 |COUNT10:3|cnt10:U3|cq10 (|COUNT10:3|cnt10:U3|:12)
- 4 - C 21 AND2 0 4 0 7 |COUNT10:3|cnt10:U3|:173
- 2 - C 21 AND2 0 2 0 1 |COUNT10:3|cnt10:U4|LPM_ADD_SUB:73|addcore:adder|:55
- 1 - C 23 AND2 0 3 0 1 |COUNT10:3|cnt10:U4|LPM_ADD_SUB:73|addcore:adder|:59
- 2 - C 23 DFFE 0 5 0 2 |COUNT10:3|cnt10:U4|cq13 (|COUNT10:3|cnt10:U4|:9)
- 3 - C 21 DFFE 0 5 0 3 |COUNT10:3|cnt10:U4|cq12 (|COUNT10:3|cnt10:U4|:10)
- 7 - C 21 DFFE 0 5 0 4 |COUNT10:3|cnt10:U4|cq11 (|COUNT10:3|cnt10:U4|:11)
- 6 - C 21 DFFE 0 3 0 5 |COUNT10:3|cnt10:U4|cq10 (|COUNT10:3|cnt10:U4|:12)
- 1 - C 21 AND2 0 4 0 7 |COUNT10:3|cnt10:U4|:173
- 8 - B 15 AND2 0 2 0 1 |COUNT10:3|cnt10:U5|LPM_ADD_SUB:73|addcore:adder|:55
- 6 - B 15 AND2 0 3 0 1 |COUNT10:3|cnt10:U5|LPM_ADD_SUB:73|addcore:adder|:59
- 7 - B 15 DFFE 0 5 0 2 |COUNT10:3|cnt10:U5|cq13 (|COUNT10:3|cnt10:U5|:9)
- 2 - B 15 DFFE 0 5 0 3 |COUNT10:3|cnt10:U5|cq12 (|COUNT10:3|cnt10:U5|:10)
- 4 - B 15 DFFE 0 5 0 4 |COUNT10:3|cnt10:U5|cq11 (|COUNT10:3|cnt10:U5|:11)
- 5 - B 15 DFFE 0 3 0 5 |COUNT10:3|cnt10:U5|cq10 (|COUNT10:3|cnt10:U5|:12)
- 3 - B 15 AND2 0 4 0 7 |COUNT10:3|cnt10:U5|:173
- 7 - B 23 AND2 0 2 0 1 |COUNT10:3|cnt10:U6|LPM_ADD_SUB:73|addcore:adder|:55
- 6 - B 23 AND2 0 3 0 1 |COUNT10:3|cnt10:U6|LPM_ADD_SUB:73|addcore:adder|:59
- 2 - B 23 DFFE 0 5 0 2 |COUNT10:3|cnt10:U6|cq13 (|COUNT10:3|cnt10:U6|:9)
- 1 - B 23 DFFE 0 5 0 3 |COUNT10:3|cnt10:U6|cq12 (|COUNT10:3|cnt10:U6|:10)
- 8 - B 23 DFFE 0 5 0 4 |COUNT10:3|cnt10:U6|cq11 (|COUNT10:3|cnt10:U6|:11)
- 3 - B 23 DFFE 0 3 0 5 |COUNT10:3|cnt10:U6|cq10 (|COUNT10:3|cnt10:U6|:12)
- 5 - B 23 AND2 0 4 0 7 |COUNT10:3|cnt10:U6|:173
- 8 - B 13 AND2 0 2 0 1 |COUNT10:3|cnt10:U7|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - B 13 AND2 0 3 0 1 |COUNT10:3|cnt10:U7|LPM_ADD_SUB:73|addcore:adder|:59
- 1 - B 13 DFFE 0 5 0 2 |COUNT10:3|cnt10:U7|cq13 (|COUNT10:3|cnt10:U7|:9)
- 2 - B 13 DFFE 0 5 0 3 |COUNT10:3|cnt10:U7|cq12 (|COUNT10:3|cnt10:U7|:10)
- 3 - B 13 DFFE 0 5 0 4 |COUNT10:3|cnt10:U7|cq11 (|COUNT10:3|cnt10:U7|:11)
- 4 - B 13 DFFE 0 3 0 5 |COUNT10:3|cnt10:U7|cq10 (|COUNT10:3|cnt10:U7|:12)
- 5 - B 13 OR2 s 0 3 0 2 |COUNT10:3|cnt10:U7|~48~1
- 6 - B 13 OR2 s 0 3 0 2 |COUNT10:3|cnt10:U7|~138~1
- 1 - C 09 OR2 ! 0 3 0 5 |DISPLAY_8_LED:4|LPM_ADD_SUB:122|addcore:adder|:67
- 6 - C 14 DFFE 1 1 1 0 |DISPLAY_8_LED:4|:41
- 8 - C 14 DFFE 1 1 1 0 |DISPLAY_8_LED:4|:43
- 4 - C 14 DFFE 1 1 1 0 |DISPLAY_8_LED:4|:45
- 3 - C 09 DFFE 1 3 0 9 |DISPLAY_8_LED:4|q5 (|DISPLAY_8_LED:4|:47)
- 4 - C 09 DFFE 1 3 0 10 |DISPLAY_8_LED:4|q4 (|DISPLAY_8_LED:4|:48)
- 8 - C 09 DFFE 1 2 0 11 |DISPLAY_8_LED:4|q3 (|DISPLAY_8_LED:4|:49)
- 5 - C 09 DFFE 1 3 0 1 |DISPLAY_8_LED:4|q2 (|DISPLAY_8_LED:4|:50)
- 7 - C 09 DFFE 1 3 0 2 |DISPLAY_8_LED:4|q1 (|DISPLAY_8_LED:4|:51)
- 6 - C 09 DFFE 1 0 0 3 |DISPLAY_8_LED:4|q0 (|DISPLAY_8_LED:4|:52)
- 1 - C 20 DFFE 1 3 0 19 |DISPLAY_8_LED:4|num3 (|DISPLAY_8_LED:4|:56)
- 1 - C 15 DFFE 1 3 0 19 |DISPLAY_8_LED:4|num2 (|DISPLAY_8_LED:4|:57)
- 1 - C 18 DFFE 1 3 0 19 |DISPLAY_8_LED:4|num1 (|DISPLAY_8_LED:4|:58)
- 1 - C 22 DFFE 1 3 0 19 |DISPLAY_8_LED:4|num0 (|DISPLAY_8_LED:4|:59)
- 2 - C 09 OR2 ! 0 2 0 1 |DISPLAY_8_LED:4|:85
- 1 - C 19 AND2 0 3 0 4 |DISPLAY_8_LED:4|:328
- 3 - C 19 AND2 0 3 0 4 |DISPLAY_8_LED:4|:335
- 4 - C 19 AND2 0 3 0 4 |DISPLAY_8_LED:4|:342
- 5 - C 19 AND2 0 3 0 4 |DISPLAY_8_LED:4|:349
- 7 - C 19 AND2 0 3 0 4 |DISPLAY_8_LED:4|:356
- 2 - C 19 AND2 0 3 0 4 |DISPLAY_8_LED:4|:363
- 8 - C 19 OR2 ! 0 3 0 4 |DISPLAY_8_LED:4|:370
- 6 - C 19 OR2 ! 0 3 0 8 |DISPLAY_8_LED:4|:377
- 4 - B 21 OR2 0 3 0 1 |DISPLAY_8_LED:4|:566
- 5 - B 21 OR2 0 3 0 1 |DISPLAY_8_LED:4|:572
- 6 - B 21 OR2 0 3 0 1 |DISPLAY_8_LED:4|:578
- 2 - B 21 OR2 0 3 0 1 |DISPLAY_8_LED:4|:584
- 3 - C 20 OR2 0 3 0 1 |DISPLAY_8_LED:4|:590
- 5 - C 20 OR2 0 3 0 1 |DISPLAY_8_LED:4|:596
- 7 - C 20 OR2 0 3 0 1 |DISPLAY_8_LED:4|:602
- 4 - B 22 OR2 0 3 0 1 |DISPLAY_8_LED:4|:614
- 5 - B 22 OR2 0 3 0 1 |DISPLAY_8_LED:4|:617
- 7 - B 22 OR2 0 3 0 1 |DISPLAY_8_LED:4|:620
- 1 - B 22 OR2 0 3 0 1 |DISPLAY_8_LED:4|:623
- 3 - C 15 OR2 0 3 0 1 |DISPLAY_8_LED:4|:626
- 5 - C 15 OR2 0 3 0 1 |DISPLAY_8_LED:4|:629
- 7 - C 15 OR2 0 3 0 1 |DISPLAY_8_LED:4|:632
- 3 - B 19 OR2 0 3 0 1 |DISPLAY_8_LED:4|:641
- 1 - B 19 OR2 0 3 0 1 |DISPLAY_8_LED:4|:644
- 4 - C 23 OR2 0 3 0 1 |DISPLAY_8_LED:4|:647
- 7 - C 23 OR2 0 3 0 1 |DISPLAY_8_LED:4|:650
- 3 - C 18 OR2 0 3 0 1 |DISPLAY_8_LED:4|:653
- 5 - C 18 OR2 0 3 0 1 |DISPLAY_8_LED:4|:656
- 7 - C 18 OR2 0 3 0 1 |DISPLAY_8_LED:4|:659
- 3 - B 16 OR2 0 3 0 1 |DISPLAY_8_LED:4|:668
- 5 - B 16 OR2 0 3 0 1 |DISPLAY_8_LED:4|:671
- 7 - B 16 OR2 0 3 0 1 |DISPLAY_8_LED:4|:674
- 4 - B 16 OR2 0 3 0 1 |DISPLAY_8_LED:4|:677
- 3 - C 22 OR2 0 3 0 1 |DISPLAY_8_LED:4|:680
- 5 - C 22 OR2 0 3 0 1 |DISPLAY_8_LED:4|:683
- 7 - C 22 OR2 0 3 0 1 |DISPLAY_8_LED:4|:686
- 1 - B 07 AND2 0 4 0 1 |DISPLAY_8_LED:4|:867
- 3 - B 07 OR2 ! 0 4 0 1 |DISPLAY_8_LED:4|:872
- 2 - B 07 AND2 0 4 0 1 |DISPLAY_8_LED:4|:877
- 7 - B 07 OR2 ! 0 4 0 1 |DISPLAY_8_LED:4|:882
- 4 - B 07 OR2 ! 0 4 0 1 |DISPLAY_8_LED:4|:887
- 5 - B 07 OR2 ! 0 4 0 1 |DISPLAY_8_LED:4|:892
- 2 - B 09 AND2 0 4 0 1 |DISPLAY_8_LED:4|:897
- 4 - B 09 OR2 ! 0 4 0 1 |DISPLAY_8_LED:4|:902
- 3 - B 09 AND2 0 4 0 1 |DISPLAY_8_LED:4|:907
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