reg32b.vhd

来自「这是我课程设计做的数字频率计的设计」· VHDL 代码 · 共 17 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg32b IS
  PORT(load:IN std_logic;
     din:IN std_logic_vector(31 DOWNTO 0);
    dout:OUT std_logic_vector(31 DOWNTO 0));
END reg32b;
ARCHITECTURE a OF reg32b IS
 BEGIN
   PROCESS(load,din)IS
    BEGIN
      IF load'EVENT AND load='1'THEN
        dout<=din;
      END IF;
   END PROCESS;
END a;