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📄 count10.rpt

📁 这是我课程设计做的数字频率计的设计
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-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = DFFE( _EQ030,  _LC2_B14, GLOBAL(!clr),  VCC,  VCC);
  _EQ030 =  _LC1_B14 & !_LC3_B16 & !_LC3_B21
         #  ena & !_LC1_B14 & !_LC3_B16 &  _LC3_B21
         # !ena &  _LC1_B14;

-- Node name is '|cnt10:U4|:10' = '|cnt10:U4|cq12' 
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = DFFE( _EQ031,  _LC2_B14, GLOBAL(!clr),  VCC,  VCC);
  _EQ031 =  ena & !_LC3_B16 &  _LC7_B14
         # !ena &  _LC8_B14;

-- Node name is '|cnt10:U4|:9' = '|cnt10:U4|cq13' 
-- Equation name is '_LC1_B16', type is buried 
_LC1_B16 = DFFE( _EQ032,  _LC2_B14, GLOBAL(!clr),  VCC,  VCC);
  _EQ032 =  _LC1_B16 & !_LC3_B16 & !_LC5_B14
         #  ena & !_LC1_B16 & !_LC3_B16 &  _LC5_B14
         # !ena &  _LC1_B16;

-- Node name is '|cnt10:U4|LPM_ADD_SUB:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = LCELL( _EQ033);
  _EQ033 =  _LC1_B14 &  _LC3_B21 &  _LC8_B14;

-- Node name is '|cnt10:U4|LPM_ADD_SUB:73|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_B14', type is buried 
_LC7_B14 = LCELL( _EQ034);
  _EQ034 = !_LC1_B14 &  _LC8_B14
         # !_LC3_B21 &  _LC8_B14
         #  _LC1_B14 &  _LC3_B21 & !_LC8_B14;

-- Node name is '|cnt10:U4|:173' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ035);
  _EQ035 = !_LC1_B14 &  _LC1_B16 &  _LC3_B21 & !_LC8_B14;

-- Node name is '|cnt10:U5|:12' = '|cnt10:U5|cq10' 
-- Equation name is '_LC7_B19', type is buried 
_LC7_B19 = DFFE( _EQ036,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ036 = !ena &  _LC7_B19
         #  ena & !_LC7_B19;

-- Node name is '|cnt10:U5|:11' = '|cnt10:U5|cq11' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = DFFE( _EQ037,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ037 =  _LC4_B16 & !_LC5_B16 & !_LC7_B19
         #  ena & !_LC4_B16 & !_LC5_B16 &  _LC7_B19
         # !ena &  _LC4_B16;

-- Node name is '|cnt10:U5|:10' = '|cnt10:U5|cq12' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = DFFE( _EQ038,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ038 =  ena & !_LC5_B16 &  _LC7_B16
         # !ena &  _LC2_B16;

-- Node name is '|cnt10:U5|:9' = '|cnt10:U5|cq13' 
-- Equation name is '_LC6_B16', type is buried 
_LC6_B16 = DFFE( _EQ039,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ039 = !_LC5_B16 &  _LC6_B16 & !_LC8_B16
         #  ena & !_LC5_B16 & !_LC6_B16 &  _LC8_B16
         # !ena &  _LC6_B16;

-- Node name is '|cnt10:U5|LPM_ADD_SUB:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = LCELL( _EQ040);
  _EQ040 =  _LC2_B16 &  _LC4_B16 &  _LC7_B19;

-- Node name is '|cnt10:U5|LPM_ADD_SUB:73|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_B16', type is buried 
_LC7_B16 = LCELL( _EQ041);
  _EQ041 =  _LC2_B16 & !_LC4_B16
         #  _LC2_B16 & !_LC7_B19
         # !_LC2_B16 &  _LC4_B16 &  _LC7_B19;

-- Node name is '|cnt10:U5|:173' 
-- Equation name is '_LC5_B16', type is buried 
_LC5_B16 = LCELL( _EQ042);
  _EQ042 = !_LC2_B16 & !_LC4_B16 &  _LC6_B16 &  _LC7_B19;

-- Node name is '|cnt10:U6|:12' = '|cnt10:U6|cq10' 
-- Equation name is '_LC8_B21', type is buried 
_LC8_B21 = DFFE( _EQ043,  _LC5_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ043 = !ena &  _LC8_B21
         #  ena & !_LC8_B21;

-- Node name is '|cnt10:U6|:11' = '|cnt10:U6|cq11' 
-- Equation name is '_LC7_B21', type is buried 
_LC7_B21 = DFFE( _EQ044,  _LC5_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ044 = !_LC2_B21 &  _LC7_B21 & !_LC8_B21
         #  ena & !_LC2_B21 & !_LC7_B21 &  _LC8_B21
         # !ena &  _LC7_B21;

-- Node name is '|cnt10:U6|:10' = '|cnt10:U6|cq12' 
-- Equation name is '_LC1_B21', type is buried 
_LC1_B21 = DFFE( _EQ045,  _LC5_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ045 =  ena & !_LC2_B21 &  _LC5_B21
         # !ena &  _LC1_B21;

-- Node name is '|cnt10:U6|:9' = '|cnt10:U6|cq13' 
-- Equation name is '_LC4_B21', type is buried 
_LC4_B21 = DFFE( _EQ046,  _LC5_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ046 = !_LC2_B21 &  _LC4_B21 & !_LC6_B21
         #  ena & !_LC2_B21 & !_LC4_B21 &  _LC6_B21
         # !ena &  _LC4_B21;

-- Node name is '|cnt10:U6|LPM_ADD_SUB:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B21', type is buried 
_LC6_B21 = LCELL( _EQ047);
  _EQ047 =  _LC1_B21 &  _LC7_B21 &  _LC8_B21;

-- Node name is '|cnt10:U6|LPM_ADD_SUB:73|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_B21', type is buried 
_LC5_B21 = LCELL( _EQ048);
  _EQ048 =  _LC1_B21 & !_LC7_B21
         #  _LC1_B21 & !_LC8_B21
         # !_LC1_B21 &  _LC7_B21 &  _LC8_B21;

-- Node name is '|cnt10:U6|:173' 
-- Equation name is '_LC2_B21', type is buried 
_LC2_B21 = LCELL( _EQ049);
  _EQ049 = !_LC1_B21 &  _LC4_B21 & !_LC7_B21 &  _LC8_B21;

-- Node name is '|cnt10:U7|:12' = '|cnt10:U7|cq10' 
-- Equation name is '_LC1_B19', type is buried 
_LC1_B19 = DFFE( _EQ050,  _LC2_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ050 = !ena &  _LC1_B19
         #  ena & !_LC1_B19;

-- Node name is '|cnt10:U7|:11' = '|cnt10:U7|cq11' 
-- Equation name is '_LC5_B19', type is buried 
_LC5_B19 = DFFE( _EQ051,  _LC2_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ051 = !_LC1_B19 & !_LC3_B19 &  _LC5_B19
         #  ena &  _LC1_B19 & !_LC3_B19 & !_LC5_B19
         # !ena &  _LC5_B19;

-- Node name is '|cnt10:U7|:10' = '|cnt10:U7|cq12' 
-- Equation name is '_LC2_B19', type is buried 
_LC2_B19 = DFFE( _EQ052,  _LC2_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ052 =  ena & !_LC3_B19 &  _LC6_B19
         # !ena &  _LC2_B19;

-- Node name is '|cnt10:U7|:9' = '|cnt10:U7|cq13' 
-- Equation name is '_LC4_B19', type is buried 
_LC4_B19 = DFFE( _EQ053,  _LC2_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ053 = !_LC3_B19 &  _LC4_B19 & !_LC8_B19
         #  ena & !_LC3_B19 & !_LC4_B19 &  _LC8_B19
         # !ena &  _LC4_B19;

-- Node name is '|cnt10:U7|LPM_ADD_SUB:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B19', type is buried 
_LC8_B19 = LCELL( _EQ054);
  _EQ054 =  _LC1_B19 &  _LC2_B19 &  _LC5_B19;

-- Node name is '|cnt10:U7|LPM_ADD_SUB:73|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_B19', type is buried 
_LC6_B19 = LCELL( _EQ055);
  _EQ055 =  _LC2_B19 & !_LC5_B19
         # !_LC1_B19 &  _LC2_B19
         #  _LC1_B19 & !_LC2_B19 &  _LC5_B19;

-- Node name is '|cnt10:U7|:48' 
-- Equation name is '_LC3_B19', type is buried 
!_LC3_B19 = _LC3_B19~NOT;
_LC3_B19~NOT = LCELL( _EQ056);
  _EQ056 =  _LC2_B19
         #  _LC5_B19
         # !_LC4_B19
         # !_LC1_B19;



Project Information                                          e:\s6\count10.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,327K

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