📄 count10.rpt
字号:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\s6\count10.rpt
count10
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
52 - - - 19 OUTPUT 0 1 0 0 carry_out
16 - - A -- OUTPUT 0 1 0 0 q0
70 - - A -- OUTPUT 0 1 0 0 q1
69 - - A -- OUTPUT 0 1 0 0 q2
71 - - A -- OUTPUT 0 1 0 0 q3
47 - - - 14 OUTPUT 0 1 0 0 q4
61 - - C -- OUTPUT 0 1 0 0 q5
50 - - - 17 OUTPUT 0 1 0 0 q6
51 - - - 18 OUTPUT 0 1 0 0 q7
79 - - - 24 OUTPUT 0 1 0 0 q8
80 - - - 23 OUTPUT 0 1 0 0 q9
72 - - A -- OUTPUT 0 1 0 0 q10
78 - - - 24 OUTPUT 0 1 0 0 q11
24 - - B -- OUTPUT 0 1 0 0 q12
23 - - B -- OUTPUT 0 1 0 0 q13
29 - - C -- OUTPUT 0 1 0 0 q14
83 - - - 13 OUTPUT 0 1 0 0 q15
66 - - B -- OUTPUT 0 1 0 0 q16
21 - - B -- OUTPUT 0 1 0 0 q17
65 - - B -- OUTPUT 0 1 0 0 q18
67 - - B -- OUTPUT 0 1 0 0 q19
64 - - B -- OUTPUT 0 1 0 0 q20
49 - - - 16 OUTPUT 0 1 0 0 q21
17 - - A -- OUTPUT 0 1 0 0 q22
48 - - - 15 OUTPUT 0 1 0 0 q23
25 - - B -- OUTPUT 0 1 0 0 q24
58 - - C -- OUTPUT 0 1 0 0 q25
81 - - - 22 OUTPUT 0 1 0 0 q26
54 - - - 21 OUTPUT 0 1 0 0 q27
62 - - C -- OUTPUT 0 1 0 0 q28
59 - - C -- OUTPUT 0 1 0 0 q29
53 - - - 20 OUTPUT 0 1 0 0 q30
60 - - C -- OUTPUT 0 1 0 0 q31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\s6\count10.rpt
count10
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 13 AND2 0 3 0 1 |cnt10:U0|LPM_ADD_SUB:73|addcore:adder|:59
- 2 - A 13 OR2 0 3 0 1 |cnt10:U0|LPM_ADD_SUB:73|addcore:adder|:68
- 4 - A 13 DFFE + 1 2 1 1 |cnt10:U0|cq13 (|cnt10:U0|:9)
- 8 - A 13 DFFE + 1 2 1 3 |cnt10:U0|cq12 (|cnt10:U0|:10)
- 5 - A 13 DFFE + 1 2 1 3 |cnt10:U0|cq11 (|cnt10:U0|:11)
- 1 - A 13 DFFE + 1 0 1 4 |cnt10:U0|cq10 (|cnt10:U0|:12)
- 6 - A 13 AND2 0 4 0 7 |cnt10:U0|:173
- 6 - B 17 AND2 0 3 0 1 |cnt10:U1|LPM_ADD_SUB:73|addcore:adder|:59
- 4 - B 17 OR2 0 3 0 1 |cnt10:U1|LPM_ADD_SUB:73|addcore:adder|:68
- 1 - B 17 DFFE 1 3 1 1 |cnt10:U1|cq13 (|cnt10:U1|:9)
- 7 - B 17 DFFE 1 3 1 3 |cnt10:U1|cq12 (|cnt10:U1|:10)
- 3 - B 17 DFFE 1 3 1 3 |cnt10:U1|cq11 (|cnt10:U1|:11)
- 3 - A 13 DFFE 1 1 1 4 |cnt10:U1|cq10 (|cnt10:U1|:12)
- 2 - B 17 AND2 0 4 0 7 |cnt10:U1|:173
- 8 - B 23 AND2 0 3 0 1 |cnt10:U2|LPM_ADD_SUB:73|addcore:adder|:59
- 1 - B 23 OR2 0 3 0 1 |cnt10:U2|LPM_ADD_SUB:73|addcore:adder|:68
- 7 - B 23 DFFE 1 3 1 1 |cnt10:U2|cq13 (|cnt10:U2|:9)
- 3 - B 23 DFFE 1 3 1 3 |cnt10:U2|cq12 (|cnt10:U2|:10)
- 5 - B 23 DFFE 1 3 1 3 |cnt10:U2|cq11 (|cnt10:U2|:11)
- 4 - B 23 DFFE 1 1 1 4 |cnt10:U2|cq10 (|cnt10:U2|:12)
- 2 - B 23 AND2 0 4 0 7 |cnt10:U2|:173
- 6 - B 14 AND2 0 3 0 1 |cnt10:U3|LPM_ADD_SUB:73|addcore:adder|:59
- 8 - B 17 OR2 0 3 0 1 |cnt10:U3|LPM_ADD_SUB:73|addcore:adder|:68
- 4 - B 14 DFFE 1 3 1 1 |cnt10:U3|cq13 (|cnt10:U3|:9)
- 5 - B 17 DFFE 1 3 1 3 |cnt10:U3|cq12 (|cnt10:U3|:10)
- 3 - B 14 DFFE 1 3 1 3 |cnt10:U3|cq11 (|cnt10:U3|:11)
- 6 - B 23 DFFE 1 1 1 4 |cnt10:U3|cq10 (|cnt10:U3|:12)
- 2 - B 14 AND2 0 4 0 7 |cnt10:U3|:173
- 5 - B 14 AND2 0 3 0 1 |cnt10:U4|LPM_ADD_SUB:73|addcore:adder|:59
- 7 - B 14 OR2 0 3 0 1 |cnt10:U4|LPM_ADD_SUB:73|addcore:adder|:68
- 1 - B 16 DFFE 1 3 1 1 |cnt10:U4|cq13 (|cnt10:U4|:9)
- 8 - B 14 DFFE 1 3 1 3 |cnt10:U4|cq12 (|cnt10:U4|:10)
- 1 - B 14 DFFE 1 3 1 3 |cnt10:U4|cq11 (|cnt10:U4|:11)
- 3 - B 21 DFFE 1 1 1 4 |cnt10:U4|cq10 (|cnt10:U4|:12)
- 3 - B 16 AND2 0 4 0 7 |cnt10:U4|:173
- 8 - B 16 AND2 0 3 0 1 |cnt10:U5|LPM_ADD_SUB:73|addcore:adder|:59
- 7 - B 16 OR2 0 3 0 1 |cnt10:U5|LPM_ADD_SUB:73|addcore:adder|:68
- 6 - B 16 DFFE 1 3 1 1 |cnt10:U5|cq13 (|cnt10:U5|:9)
- 2 - B 16 DFFE 1 3 1 3 |cnt10:U5|cq12 (|cnt10:U5|:10)
- 4 - B 16 DFFE 1 3 1 3 |cnt10:U5|cq11 (|cnt10:U5|:11)
- 7 - B 19 DFFE 1 1 1 4 |cnt10:U5|cq10 (|cnt10:U5|:12)
- 5 - B 16 AND2 0 4 0 7 |cnt10:U5|:173
- 6 - B 21 AND2 0 3 0 1 |cnt10:U6|LPM_ADD_SUB:73|addcore:adder|:59
- 5 - B 21 OR2 0 3 0 1 |cnt10:U6|LPM_ADD_SUB:73|addcore:adder|:68
- 4 - B 21 DFFE 1 3 1 1 |cnt10:U6|cq13 (|cnt10:U6|:9)
- 1 - B 21 DFFE 1 3 1 3 |cnt10:U6|cq12 (|cnt10:U6|:10)
- 7 - B 21 DFFE 1 3 1 3 |cnt10:U6|cq11 (|cnt10:U6|:11)
- 8 - B 21 DFFE 1 1 1 4 |cnt10:U6|cq10 (|cnt10:U6|:12)
- 2 - B 21 AND2 0 4 0 7 |cnt10:U6|:173
- 8 - B 19 AND2 0 3 0 1 |cnt10:U7|LPM_ADD_SUB:73|addcore:adder|:59
- 6 - B 19 OR2 0 3 0 1 |cnt10:U7|LPM_ADD_SUB:73|addcore:adder|:68
- 4 - B 19 DFFE 1 3 1 1 |cnt10:U7|cq13 (|cnt10:U7|:9)
- 2 - B 19 DFFE 1 3 1 3 |cnt10:U7|cq12 (|cnt10:U7|:10)
- 5 - B 19 DFFE 1 3 1 3 |cnt10:U7|cq11 (|cnt10:U7|:11)
- 1 - B 19 DFFE 1 1 1 4 |cnt10:U7|cq10 (|cnt10:U7|:12)
- 3 - B 19 OR2 ! 0 4 1 3 |cnt10:U7|:48
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\s6\count10.rpt
count10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 8/ 96( 8%) 0/ 48( 0%) 17/ 48( 35%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\s6\count10.rpt
count10
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 7 |cnt10:U0|:173
LCELL 7 |cnt10:U1|:173
LCELL 7 |cnt10:U2|:173
LCELL 7 |cnt10:U3|:173
LCELL 7 |cnt10:U4|:173
LCELL 7 |cnt10:U5|:173
LCELL 7 |cnt10:U6|:173
INPUT 4 clk
Device-Specific Information: e:\s6\count10.rpt
count10
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 32 clr
Device-Specific Information: e:\s6\count10.rpt
count10
** EQUATIONS **
clk : INPUT;
clr : INPUT;
ena : INPUT;
-- Node name is 'carry_out'
-- Equation name is 'carry_out', type is output
carry_out = _LC3_B19;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC1_A13;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC5_A13;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC8_A13;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC4_A13;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC3_A13;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC3_B17;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC7_B17;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = _LC1_B17;
-- Node name is 'q8'
-- Equation name is 'q8', type is output
q8 = _LC4_B23;
-- Node name is 'q9'
-- Equation name is 'q9', type is output
q9 = _LC5_B23;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = _LC3_B23;
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