reg32b.rpt

这是我课程设计做的数字频率计的设计

-- Node name is 'dout18' 
-- Equation name is 'dout18', type is output 
dout18   =  _LC2_B4;

-- Node name is 'dout19' 
-- Equation name is 'dout19', type is output 
dout19   =  _LC6_B7;

-- Node name is 'dout20' 
-- Equation name is 'dout20', type is output 
dout20   =  _LC4_A9;

-- Node name is 'dout21' 
-- Equation name is 'dout21', type is output 
dout21   =  _LC2_A3;

-- Node name is 'dout22' 
-- Equation name is 'dout22', type is output 
dout22   =  _LC5_B5;

-- Node name is 'dout23' 
-- Equation name is 'dout23', type is output 
dout23   =  _LC2_A6;

-- Node name is 'dout24' 
-- Equation name is 'dout24', type is output 
dout24   =  _LC3_C21;

-- Node name is 'dout25' 
-- Equation name is 'dout25', type is output 
dout25   =  _LC7_B15;

-- Node name is 'dout26' 
-- Equation name is 'dout26', type is output 
dout26   =  _LC5_A13;

-- Node name is 'dout27' 
-- Equation name is 'dout27', type is output 
dout27   =  _LC1_B3;

-- Node name is 'dout28' 
-- Equation name is 'dout28', type is output 
dout28   =  _LC2_C19;

-- Node name is 'dout29' 
-- Equation name is 'dout29', type is output 
dout29   =  _LC4_A17;

-- Node name is 'dout30' 
-- Equation name is 'dout30', type is output 
dout30   =  _LC5_A11;

-- Node name is 'dout31' 
-- Equation name is 'dout31', type is output 
dout31   =  _LC1_C7;

-- Node name is ':34' 
-- Equation name is '_LC1_C7', type is buried 
_LC1_C7  = DFFE( din31, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':36' 
-- Equation name is '_LC5_A11', type is buried 
_LC5_A11 = DFFE( din30, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':38' 
-- Equation name is '_LC4_A17', type is buried 
_LC4_A17 = DFFE( din29, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':40' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = DFFE( din28, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':42' 
-- Equation name is '_LC1_B3', type is buried 
_LC1_B3  = DFFE( din27, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':44' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = DFFE( din26, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':46' 
-- Equation name is '_LC7_B15', type is buried 
_LC7_B15 = DFFE( din25, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':48' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = DFFE( din24, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':50' 
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = DFFE( din23, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':52' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = DFFE( din22, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':54' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = DFFE( din21, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':56' 
-- Equation name is '_LC4_A9', type is buried 
_LC4_A9  = DFFE( din20, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':58' 
-- Equation name is '_LC6_B7', type is buried 
_LC6_B7  = DFFE( din19, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':60' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = DFFE( din18, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':62' 
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = DFFE( din17, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':64' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = DFFE( din16, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':66' 
-- Equation name is '_LC8_A4', type is buried 
_LC8_A4  = DFFE( din15, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':68' 
-- Equation name is '_LC2_C6', type is buried 
_LC2_C6  = DFFE( din14, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':70' 
-- Equation name is '_LC1_A21', type is buried 
_LC1_A21 = DFFE( din13, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':72' 
-- Equation name is '_LC1_C18', type is buried 
_LC1_C18 = DFFE( din12, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':74' 
-- Equation name is '_LC4_B6', type is buried 
_LC4_B6  = DFFE( din11, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':76' 
-- Equation name is '_LC4_B17', type is buried 
_LC4_B17 = DFFE( din10, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':78' 
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = DFFE( din9, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':80' 
-- Equation name is '_LC5_C3', type is buried 
_LC5_C3  = DFFE( din8, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':82' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = DFFE( din7, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':84' 
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = DFFE( din6, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':86' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = DFFE( din5, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':88' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = DFFE( din4, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':90' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = DFFE( din3, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':92' 
-- Equation name is '_LC5_B17', type is buried 
_LC5_B17 = DFFE( din2, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':94' 
-- Equation name is '_LC4_A3', type is buried 
_LC4_A3  = DFFE( din1, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is ':96' 
-- Equation name is '_LC1_A22', type is buried 
_LC1_A22 = DFFE( din0, GLOBAL( load),  VCC,  VCC,  VCC);



Project Information                                           e:\s6\reg32b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,516K