control.vhd

来自「这是我课程设计做的数字频率计的设计」· VHDL 代码 · 共 34 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY control IS
  PORT(reset:IN std_logic;
       clk:IN std_logic;
       cnt_en:OUT std_logic;
       clr_cnt:OUT std_logic;
       load:OUT std_logic);
END control;
ARCHITECTURE a OF control IS
 SIGNAL div2clk:std_logic;
 BEGIN
   PROCESS(reset,clk)IS
    BEGIN
      IF reset='1' THEN
         div2clk<='0';
      ELSIF clk'event AND clk='1' THEN
         div2clk<=NOT div2clk;
      END IF;
   END PROCESS;
   PROCESS(div2clk,reset,clk)IS
    BEGIN
      IF reset='1' THEN
         clr_cnt<='1';
      ELSE  
         clr_cnt<=NOT( clk OR div2clk);
      END IF;
   END PROCESS;
  cnt_en<=div2clk;
  load<=NOT div2clk;
END a;