count10.vhd

这是我课程设计做的数字频率计的设计

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY count10 IS
  PORT(clk:IN std_logic;
       clr:IN std_logic;
       ena:IN std_logic;
       q:OUT std_logic_vector(31 DOWNTO 0);
       carry_out:OUT std_logic);
END count10;
ARCHITECTURE a OF count10 IS
COMPONENT cnt10 IS
  PORT(clk:IN std_logic;
       clr:IN std_logic;
       ena:IN std_logic;
       cq:OUT std_logic_vector(3 DOWNTO 0);
       carry_out:OUT std_logic);
END COMPONENT;
SIGNAL s0,s1,s2,s3,s4,s5,s6:std_logic;
BEGIN 
U0:cnt10 PORT MAP(clk,clr,ena,cq=>q(3 DOWNTO 0),s0);
U1:cnt10 PORT MAP(s0,clr,ena,cq=>q(7 DOWNTO 4),s1);
U2:cnt10 PORT MAP(s1,clr,ena,cq=>q(11 DOWNTO 8),s2);
U3:cnt10 PORT MAP(s2,clr,ena,cq=>q(15 DOWNTO 12),s3);
U4:cnt10 PORT MAP(s3,clr,ena,cq=>q(19 DOWNTO 16),s4);
U5:cnt10 PORT MAP(s4,clr,ena,cq=>q(23 DOWNTO 20),s5);
U6:cnt10 PORT MAP(s5,clr,ena,cq=>q(27 DOWNTO 24),s6);
U7:cnt10 PORT MAP(s6,clr,ena,cq=>q(31 DOWNTO 28),carry_out);
END a;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY cnt10 IS
  PORT(clk:IN std_logic;
       clr:IN std_logic;
       ena:IN std_logic;
       cq:OUT std_logic_vector(3 DOWNTO 0);
       carry_out:OUT std_logic);
END cnt10;
ARCHITECTURE b OF cnt10 IS
SIGNAL cq1:std_logic_vector(3 DOWNTO 0);
BEGIN 
PROCESS(clk,clr,ena)IS
BEGIN
  IF clr='1'THEN cq1<="0000";
  ELSIF clk'event AND clk='1'THEN
    IF ena='1'THEN
       IF cq1="1001"THEN 
          cq1<="0000";
       ELSE  
          cq1<=cq1+'1';
       END IF;
    END IF;
  END IF;
END PROCESS;
PROCESS(cq1)IS
BEGIN
  IF cq1="1001" THEN 
     carry_out<='1';
  ELSE 
     carry_out<='0';
  END IF;
END PROCESS;
  cq<=cq1;
END b;