dul_port_c1024.v

DE2开发板电视接收机源码verilog

module dul_port_c1024(
	input  [7:0]iDATA,
	input  iHSYNC,
	input  iHSYNCx2,
	input  Y_CLOCK,
	input  Y_CLOCKx2,
	input  field,
	input  VS,
	output [7:0]oDATA
);

/////////address counter////////////
	reg I;
	always@(negedge iHSYNC) if (VS) I=field; else I=~I;
	reg  [9:0]counter;
	always@(posedge iHSYNC or posedge Y_CLOCK)begin
		if (iHSYNC)counter=0;else counter=counter+1;
	end
	reg  [9:0]counterx2;
	always@(negedge iHSYNCx2 or posedge Y_CLOCKx2)begin
		if (!iHSYNCx2) counterx2=0; else counterx2=counterx2+1;
	end

/////////2-port address assign//////
	wire [7:0]DATA_a,DATA_b; 
	wire I_a= I;
	wire I_b=~I;
	wire [9:0]COUNTER_a= (I)?counter:counterx2;
	wire [9:0]COUNTER_b=(!I)?counter:counterx2;
	wire CLOCK_a= (I)?~Y_CLOCK:~Y_CLOCKx2;
	wire CLOCK_b=(!I)?~Y_CLOCK:~Y_CLOCKx2;
	
//////dual-port RAM//////
	RAM2 u2(
		.data_a		(iDATA),  //a port
		.wren_a		(I_a),
		.address_a	(COUNTER_a),
		.clock_a	(CLOCK_a),
		.q_a		(DATA_a),
		.data_b		(iDATA),  //b port
		.wren_b		(I_b),
		.address_b	(COUNTER_b),
		.clock_b	(CLOCK_b),
		.q_b		(DATA_b)
	);

////datax2 output/////
	assign  oDATA=(!I)?DATA_a:DATA_b;
	
endmodule