create_200m.vhd

本代码用于产生FPGA内部的一个200Mhz的时钟

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 8.2.03i
--  \   \         Application : xaw2vhdl
--  /   /         Filename : create_200m.vhd
-- /___/   /\     Timestamp : 03/16/2007 10:06:37
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: xaw2vhdl-intstyle E:/integration_module/spi_receive_60/create_200m.xaw -st create_200m.vhd
--Design Name: create_200m
--Device: xc4vfx60-11ff1152
--
-- Module create_200m
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
----------------------------------------------------该模块用于提供200MHZ的标准时钟-----------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity create_200m is
   port ( CLKIN_IN   : in    std_logic; 
          RST_IN     : in    std_logic; 
          CLK0_OUT   : out   std_logic; 
          CLK2X_OUT  : out   std_logic; 
          LOCKED_OUT : out   std_logic);
end create_200m;

architecture BEHAVIORAL of create_200m is
   signal CLKFB_IN   : std_logic;
   signal CLK0_BUF   : std_logic;
   signal CLK2X_BUF  : std_logic;
   signal GND1       : std_logic_vector (6 downto 0);
   signal GND2       : std_logic_vector (15 downto 0);
   signal GND3       : std_logic;
   component BUFG
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   
   -- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.49 ns
   -- Period Jitter (unit interval) for block DCM_ADV_INST = 0.03 UI
   -- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.22 ns
   component DCM_ADV
      generic( CLK_FEEDBACK : string :=  "1X";
               CLKDV_DIVIDE : real :=  2.0;
               CLKFX_DIVIDE : integer :=  1;
               CLKFX_MULTIPLY : integer :=  4;
               CLKIN_DIVIDE_BY_2 : boolean :=  FALSE;
               CLKIN_PERIOD : real :=  10.0;
               CLKOUT_PHASE_SHIFT : string :=  "NONE";
               DCM_AUTOCALIBRATION : boolean :=  TRUE;
               DCM_PERFORMANCE_MODE : string :=  "MAX_SPEED";
               DESKEW_ADJUST : string :=  "SYSTEM_SYNCHRONOUS";
               DFS_FREQUENCY_MODE : string :=  "LOW";
               DLL_FREQUENCY_MODE : string :=  "LOW";
               DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
               FACTORY_JF : bit_vector :=  x"F0F0";
               PHASE_SHIFT : integer :=  0;
               STARTUP_WAIT : boolean :=  FALSE);
      port ( CLKIN    : in    std_logic; 
             CLKFB    : in    std_logic; 
             DADDR    : in    std_logic_vector (6 downto 0); 
             DI       : in    std_logic_vector (15 downto 0); 
             DWE      : in    std_logic; 
             DEN      : in    std_logic; 
             DCLK     : in    std_logic; 
             RST      : in    std_logic; 
             PSEN     : in    std_logic; 
             PSINCDEC : in    std_logic; 
             PSCLK    : in    std_logic; 
             CLK0     : out   std_logic; 
             CLK90    : out   std_logic; 
             CLK180   : out   std_logic; 
             CLK270   : out   std_logic; 
             CLKDV    : out   std_logic; 
             CLK2X    : out   std_logic; 
             CLK2X180 : out   std_logic; 
             CLKFX    : out   std_logic; 
             CLKFX180 : out   std_logic; 
             DRDY     : out   std_logic; 
             DO       : out   std_logic_vector (15 downto 0); 
             LOCKED   : out   std_logic; 
             PSDONE   : out   std_logic);
   end component;
   
begin
   GND1(6 downto 0) <= "0000000";
   GND2(15 downto 0) <= "0000000000000000";
   GND3 <= '0';
   CLK0_OUT <= CLKFB_IN;
   CLK0_BUFG_INST : BUFG
      port map (I=>CLK0_BUF,
                O=>CLKFB_IN);
   
   CLK2X_BUFG_INST : BUFG
      port map (I=>CLK2X_BUF,
                O=>CLK2X_OUT);
   
   DCM_ADV_INST : DCM_ADV
   generic map( CLK_FEEDBACK => "1X",
            CLKDV_DIVIDE => 2.0,
            CLKFX_DIVIDE => 1,
            CLKFX_MULTIPLY => 4,
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 10.0,
            CLKOUT_PHASE_SHIFT => "NONE",
            DCM_AUTOCALIBRATION => TRUE,
            DCM_PERFORMANCE_MODE => "MAX_SPEED",
            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "LOW",
            DLL_FREQUENCY_MODE => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"F0F0",
            PHASE_SHIFT => 0,
            STARTUP_WAIT => FALSE)
      port map (CLKFB=>CLKFB_IN,
                CLKIN=>CLKIN_IN,
                DADDR(6 downto 0)=>GND1(6 downto 0),
                DCLK=>GND3,
                DEN=>GND3,
                DI(15 downto 0)=>GND2(15 downto 0),
                DWE=>GND3,
                PSCLK=>GND3,
                PSEN=>GND3,
                PSINCDEC=>GND3,
                RST=>RST_IN,
                CLKDV=>open,
                CLKFX=>open,
                CLKFX180=>open,
                CLK0=>CLK0_BUF,
                CLK2X=>CLK2X_BUF,
                CLK2X180=>open,
                CLK90=>open,
                CLK180=>open,
                CLK270=>open,
                DO=>open,
                DRDY=>open,
                LOCKED=>LOCKED_OUT,
                PSDONE=>open);
   
end BEHAVIORAL;