📄 v_transfer.vhd
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LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY v_transfer IS --由9011传给9034的信号,实现直入直出 PORT ( HRQE1 : IN STD_LOGIC_VECTOR (23 DOWNTO 6); HRQE2 : IN STD_LOGIC_VECTOR (3 DOWNTO 2); HRODCK : IN STD_LOGIC; HRDE : IN STD_LOGIC; MODE : IN STD_LOGIC;--0编码,1解码 HRHSYNC : IN STD_LOGIC; HRVSYNC : IN STD_LOGIC; HRSCDT : IN STD_LOGIC; HRINT : IN STD_LOGIC; CFGDONE : IN STD_LOGIC; HRHPD : IN STD_LOGIC; -- VDTI : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); VICLK : OUT STD_LOGIC; HTD1 : OUT STD_LOGIC_VECTOR (23 DOWNTO 6); HTD2 : OUT STD_LOGIC_VECTOR (3 DOWNTO 2); HTIDCK : OUT STD_LOGIC; HTDE : OUT STD_LOGIC; HTHSYNC : OUT STD_LOGIC; HTVSYNC : OUT STD_LOGIC );END v_transfer;architecture art of v_transfer is begin HTIDCK <= HRODCK; process(HRDE, HRODCK, CFGDONE) --CFGDONE 标志9011 9034配置完成。 begin if(HRODCK'event and HRODCK='1' and CFGDONE = '1')then HTD1(23 downto 6) <= HRQE1(23 downto 6); HTD2(3 downto 2) <= HRQE2(3 downto 2);-- HTIDCK <= HRODCK; HTDE <= HRDE; HTHSYNC <= HRHSYNC; HTVSYNC <= HRVSYNC; --低有效复位信号 end if; end process;end;
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