v_transfer2.vhd

来自「自己写的iic配置芯片的源程序」· VHDL 代码 · 共 35 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY v_transfer2 IS    --由cpu输出的视频信号
	PORT
	(
		   VDTO     : IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
		  VOCLK 	: IN  STD_LOGIC;
		   MODE  	: IN  STD_LOGIC;
		    HTD     : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
		 HTIDCK	    : OUT STD_LOGIC;
		   HTDE     : OUT STD_LOGIC;
		 HTHSYNC    : OUT STD_LOGIC;
	    HTVSYNC    : OUT STD_LOGIC	
	);
END v_transfer2;
architecture art of v_transfer2 is
 begin
 -- process(VOCLK,MODE)
 -- begin
--    HTRESET <='1';--低有效复位信号
      HTIDCK<=VOCLK; 
      HTD(23 downto 0)<="111100001111111100000000";
    
   -- if(VOCLK'event and VOCLK='1')then
       --if(MODE='1')then
      -- HTD(11 downto 4)<=VDTO(7 downto 0);
       -- HTD(19 downto 12)<=VDTO(15 downto 8);
        HTDE<='1';
    --   else
    --    HTDE<='0';
     --  end if;
 --   end if;
 -- end process;
 end;