v_fpga.sim.rpt

自己写的iic配置芯片的源程序

; |v_fpga|sim_i2c:inst3|state.wr23_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr23_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~437                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~437                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|WideOr156~438                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~438                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr16_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr16_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr16_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr16_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr10_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr10_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr10_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr10_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~439                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~439                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr12_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr12_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr12_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr12_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.start_d                                                    ; |v_fpga|sim_i2c:inst3|state.start_d                                               ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~440                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~440                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr1_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr1_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr1_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr1_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr4_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr4_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr4_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr4_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~441                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~441                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr6_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr6_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr6_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr6_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr7_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr7_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr7_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr7_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~442                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~442                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr8_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr8_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr8_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr8_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~443                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~443                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|WideOr156~444                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~444                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.ack1_a                                                     ; |v_fpga|sim_i2c:inst3|state.ack1_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.ack1_d                                                     ; |v_fpga|sim_i2c:inst3|state.ack1_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.ack2_a                                                     ; |v_fpga|sim_i2c:inst3|state.ack2_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~445                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~445                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.ack2_d                                                     ; |v_fpga|sim_i2c:inst3|state.ack2_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.ack3_a                                                     ; |v_fpga|sim_i2c:inst3|state.ack3_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~446                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~446                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.start_a                                                    ; |v_fpga|sim_i2c:inst3|state.start_a                                               ; regout           ;
; |v_fpga|sim_i2c:inst3|iscl~0                                                           ; |v_fpga|sim_i2c:inst3|iscl~0                                                      ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr23_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr23_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr23_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr23_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~813                                                  ; |v_fpga|sim_i2c:inst3|Selector161~813                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr10_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr10_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr10_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr10_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~814                                                  ; |v_fpga|sim_i2c:inst3|Selector161~814                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr20_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr20_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr20_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr20_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~815                                                  ; |v_fpga|sim_i2c:inst3|Selector161~815                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector161~816                                                  ; |v_fpga|sim_i2c:inst3|Selector161~816                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr12_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr12_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr12_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr12_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~817                                                  ; |v_fpga|sim_i2c:inst3|Selector161~817                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector161~818                                                  ; |v_fpga|sim_i2c:inst3|Selector161~818                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr5_b                                                      ; |v_fpga|sim_i2c:inst3|state.wr5_b                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr5_c                                                      ; |v_fpga|sim_i2c:inst3|state.wr5_c                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~819                                                  ; |v_fpga|sim_i2c:inst3|Selector161~819                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr15_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr15_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr15_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr15_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~820                                                  ; |v_fpga|sim_i2c:inst3|Selector161~820                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector161~821                                                  ; |v_fpga|sim_i2c:inst3|Selector161~821                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr18_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr18_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr18_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr18_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~822                                                  ; |v_fpga|sim_i2c:inst3|Selector161~822                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr9_b                                                      ; |v_fpga|sim_i2c:inst3|state.wr9_b                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr9_c                                                      ; |v_fpga|sim_i2c:inst3|state.wr9_c                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~823                                                  ; |v_fpga|sim_i2c:inst3|Selector161~823                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector161~824                                                  ; |v_fpga|sim_i2c:inst3|Selector161~824                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr14_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr14_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr14_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr14_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~825                                                  ; |v_fpga|sim_i2c:inst3|Selector161~825                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr16_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr16_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr16_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr16_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~826                                                  ; |v_fpga|sim_i2c:inst3|Selector161~826                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector161~827                                                  ; |v_fpga|sim_i2c:inst3|Selector161~827                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr19_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr19_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr19_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr19_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~828                                                  ; |v_fpga|sim_i2c:inst3|Selector161~828                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr17_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr17_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr17_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr17_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~829                                                  ; |v_fpga|sim_i2c:inst3|Selector161~829                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector161~830                                                  ; |v_fpga|sim_i2c:inst3|Selector161~830                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr24_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr24_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr24_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr24_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~831                                                  ; |v_fpga|sim_i2c:inst3|Selector161~831                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr21_b                                                     ; |v_fpga|sim_i2c:inst3|state.wr21_b                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr21_c                                                     ; |v_fpga|sim_i2c:inst3|state.wr21_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|Selector161~832                                                  ; |v_fpga|sim_i2c:inst3|Selector161~832                                             ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector161~833                                                  ; |v_fpga|sim_i2c:inst3|Selector161~833                                             ; combout          ;