v_fpga.sim.rpt

自己写的iic配置芯片的源程序

; |v_fpga|counter:inst6|Add1~415                                                         ; |v_fpga|counter:inst6|Add1~415                                                    ; combout          ;
; |v_fpga|counter:inst6|Add1~415                                                         ; |v_fpga|counter:inst6|Add1~416                                                    ; cout             ;
; |v_fpga|counter:inst6|Add1~417                                                         ; |v_fpga|counter:inst6|Add1~417                                                    ; combout          ;
; |v_fpga|sim_i2c:inst3|state.ack3_d                                                     ; |v_fpga|sim_i2c:inst3|state.ack3_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.tristate                                                   ; |v_fpga|sim_i2c:inst3|state.tristate                                              ; regout           ;
; |v_fpga|sim_i2c:inst3|state.idle~28                                                    ; |v_fpga|sim_i2c:inst3|state.idle~28                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|WideOr152                                                        ; |v_fpga|sim_i2c:inst3|WideOr152                                                   ; combout          ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vi[0]                                         ; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vi[0]                                    ; regout           ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vi[1]                                         ; |v_fpga|sim_i2c:inst3|LessThan0~68                                                ; combout          ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vi[3]                                         ; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vi[3]                                    ; regout           ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vi[2]                                         ; |v_fpga|sim_i2c:inst3|LessThan0~69                                                ; combout          ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vcycle[2]                                     ; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vcycle[2]                                ; regout           ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vcycle[1]                                     ; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vcycle[1]                                ; regout           ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vcycle[3]                                     ; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vcycle[3]                                ; regout           ;
; |v_fpga|sim_i2c:inst3|\nxt_state_decoder:vcycle[0]                                     ; |v_fpga|sim_i2c:inst3|Equal0~130                                                  ; combout          ;
; |v_fpga|sim_i2c:inst3|Equal0~134                                                       ; |v_fpga|sim_i2c:inst3|Equal0~134                                                  ; combout          ;
; |v_fpga|sim_i2c:inst3|Selector0~73                                                     ; |v_fpga|sim_i2c:inst3|Selector0~73                                                ; combout          ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[7]  ; portadataout0    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[1]  ; portadataout1    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[6]  ; portadataout2    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[5]  ; portadataout3    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[4]  ; portadataout4    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[3]  ; portadataout5    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[2]  ; portadataout6    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[0]  ; portadataout7    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[14] ; portadataout8    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[12] ; portadataout9    ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[9]  ; portadataout10   ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[16] ; portadataout11   ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[15] ; portadataout12   ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[8]  ; portadataout13   ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[10] ; portadataout14   ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[11] ; portadataout15   ;
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ram_block1a7 ; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|q_a[13] ; portadataout16   ;
; |v_fpga|sim_i2c:inst3|Selector7~28                                                     ; |v_fpga|sim_i2c:inst3|Selector7~28                                                ; combout          ;
; |v_fpga|sim_i2c:inst3|Mux6~44                                                          ; |v_fpga|sim_i2c:inst3|Mux6~44                                                     ; combout          ;
; |v_fpga|sim_i2c:inst3|SCLo                                                             ; |v_fpga|sim_i2c:inst3|SCLo                                                        ; regout           ;
; |v_fpga|sim_i2c:inst3|SCLo~en                                                          ; |v_fpga|sim_i2c:inst3|SCLo~en                                                     ; regout           ;
; |v_fpga|sim_i2c:inst3|SDAo                                                             ; |v_fpga|sim_i2c:inst3|SDAo                                                        ; regout           ;
; |v_fpga|sim_i2c:inst3|SDAo~en                                                          ; |v_fpga|sim_i2c:inst3|SDAo~en                                                     ; regout           ;
; |v_fpga|sim_i2c:inst3|state.ack3_c                                                     ; |v_fpga|sim_i2c:inst3|state.ack3_c                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|cycle[0]                                                         ; |v_fpga|sim_i2c:inst3|cycle[0]                                                    ; regout           ;
; |v_fpga|sim_i2c:inst3|cycle[1]                                                         ; |v_fpga|sim_i2c:inst3|cycle[1]                                                    ; regout           ;
; |v_fpga|sim_i2c:inst3|cycle[3]                                                         ; |v_fpga|sim_i2c:inst3|cycle[3]                                                    ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr21_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr21_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr21_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr21_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr2_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr2_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr2_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr2_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr3_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr3_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr3_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr3_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~428                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~428                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr18_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr18_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr18_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr18_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~429                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~429                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|WideOr156~430                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~430                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr11_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr11_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr11_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr11_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr9_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr9_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr9_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr9_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~431                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~431                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr22_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr22_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr22_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr22_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr5_a                                                      ; |v_fpga|sim_i2c:inst3|state.wr5_a                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr5_d                                                      ; |v_fpga|sim_i2c:inst3|state.wr5_d                                                 ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~432                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~432                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr17_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr17_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr17_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr17_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr19_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr19_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr19_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr19_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~433                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~433                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr15_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr15_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr15_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr15_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr24_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr24_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr24_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr24_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~434                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~434                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|WideOr156~435                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~435                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr20_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr20_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr20_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr20_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr14_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr14_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr14_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr14_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr13_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr13_a                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|state.wr13_d                                                     ; |v_fpga|sim_i2c:inst3|state.wr13_d                                                ; regout           ;
; |v_fpga|sim_i2c:inst3|WideOr156~436                                                    ; |v_fpga|sim_i2c:inst3|WideOr156~436                                               ; combout          ;
; |v_fpga|sim_i2c:inst3|state.wr23_a                                                     ; |v_fpga|sim_i2c:inst3|state.wr23_a                                                ; regout           ;