📄 v_fpga.sim.rpt
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+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------------------------+
; |v_fpga|sim_i2c:inst3|altsyncram:Mux0_rtl_0|altsyncram_abu:auto_generated|ALTSYNCRAM ;
+--------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 60.90 % ;
; Total nodes checked ; 603 ;
; Total output ports checked ; 688 ;
; Total output ports with complete 1/0-value coverage ; 419 ;
; Total output ports with no 1/0-value coverage ; 261 ;
; Total output ports with no 1-value coverage ; 263 ;
; Total output ports with no 0-value coverage ; 267 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; |v_fpga|sim_i2c:inst3|WrDone ; |v_fpga|sim_i2c:inst3|WrDone ; regout ;
; |v_fpga|counter:inst6|a[4] ; |v_fpga|counter:inst6|a[4] ; regout ;
; |v_fpga|counter:inst6|a[1] ; |v_fpga|counter:inst6|a[1] ; regout ;
; |v_fpga|counter:inst6|a[0] ; |v_fpga|counter:inst6|a[0] ; regout ;
; |v_fpga|counter:inst6|a[3] ; |v_fpga|counter:inst6|a[3] ; regout ;
; |v_fpga|counter:inst6|a[2] ; |v_fpga|counter:inst6|Equal0~48 ; combout ;
; |v_fpga|counter:inst6|a[2] ; |v_fpga|counter:inst6|a[2] ; regout ;
; |v_fpga|counter:inst6|a[5] ; |v_fpga|counter:inst6|a[5] ; regout ;
; |v_fpga|counter:inst6|b[0] ; |v_fpga|counter:inst6|b[0] ; regout ;
; |v_fpga|counter:inst6|b[1] ; |v_fpga|counter:inst6|b[1] ; regout ;
; |v_fpga|counter:inst6|b[2] ; |v_fpga|counter:inst6|b[2] ; regout ;
; |v_fpga|counter:inst6|b[3] ; |v_fpga|counter:inst6|Equal1~290 ; combout ;
; |v_fpga|counter:inst6|Equal1~294 ; |v_fpga|counter:inst6|Equal1~294 ; combout ;
; |v_fpga|counter:inst6|HRRESET ; |v_fpga|counter:inst6|Equal1~298 ; combout ;
; |v_fpga|sim_i2c:inst3|state.stop_a ; |v_fpga|sim_i2c:inst3|state.stop_a ; regout ;
; |v_fpga|sim_i2c:inst3|state.stop_b ; |v_fpga|sim_i2c:inst3|state.stop_b ; regout ;
; |v_fpga|sim_i2c:inst3|state.idle ; |v_fpga|sim_i2c:inst3|state.idle ; regout ;
; |v_fpga|sim_i2c:inst3|state.stop_c ; |v_fpga|sim_i2c:inst3|state.stop_c ; regout ;
; |v_fpga|sim_i2c:inst3|i[1] ; |v_fpga|sim_i2c:inst3|Add1~148 ; combout ;
; |v_fpga|sim_i2c:inst3|i[1] ; |v_fpga|sim_i2c:inst3|i[1] ; regout ;
; |v_fpga|sim_i2c:inst3|i[4] ; |v_fpga|sim_i2c:inst3|Add1~149 ; combout ;
; |v_fpga|sim_i2c:inst3|i[3] ; |v_fpga|sim_i2c:inst3|Add1~150 ; combout ;
; |v_fpga|sim_i2c:inst3|i[3] ; |v_fpga|sim_i2c:inst3|i[3] ; regout ;
; |v_fpga|sim_i2c:inst3|i[2] ; |v_fpga|sim_i2c:inst3|Add1~151 ; combout ;
; |v_fpga|sim_i2c:inst3|i[2] ; |v_fpga|sim_i2c:inst3|i[2] ; regout ;
; |v_fpga|sim_i2c:inst3|Add1~152 ; |v_fpga|sim_i2c:inst3|Add1~152 ; combout ;
; |v_fpga|counter:inst6|Add0~87 ; |v_fpga|counter:inst6|Add0~87 ; combout ;
; |v_fpga|counter:inst6|Add0~87 ; |v_fpga|counter:inst6|Add0~88 ; cout0 ;
; |v_fpga|counter:inst6|Add0~89 ; |v_fpga|counter:inst6|Add0~89 ; combout ;
; |v_fpga|counter:inst6|Add0~89 ; |v_fpga|counter:inst6|Add0~90 ; cout0 ;
; |v_fpga|counter:inst6|Add0~89 ; |v_fpga|counter:inst6|Add0~90COUT1 ; cout1 ;
; |v_fpga|counter:inst6|Add0~91 ; |v_fpga|counter:inst6|Add0~91 ; combout ;
; |v_fpga|counter:inst6|Add0~91 ; |v_fpga|counter:inst6|Add0~92 ; cout0 ;
; |v_fpga|counter:inst6|Add0~91 ; |v_fpga|counter:inst6|Add0~92COUT1 ; cout1 ;
; |v_fpga|counter:inst6|Add0~93 ; |v_fpga|counter:inst6|Add0~93 ; combout ;
; |v_fpga|counter:inst6|Add0~93 ; |v_fpga|counter:inst6|Add0~94 ; cout0 ;
; |v_fpga|counter:inst6|Add0~93 ; |v_fpga|counter:inst6|Add0~94COUT1 ; cout1 ;
; |v_fpga|counter:inst6|Add0~95 ; |v_fpga|counter:inst6|Add0~95 ; combout ;
; |v_fpga|counter:inst6|Add0~95 ; |v_fpga|counter:inst6|Add0~96 ; cout ;
; |v_fpga|counter:inst6|Add0~97 ; |v_fpga|counter:inst6|Add0~97 ; combout ;
; |v_fpga|counter:inst6|Add1~409 ; |v_fpga|counter:inst6|Add1~409 ; combout ;
; |v_fpga|counter:inst6|Add1~409 ; |v_fpga|counter:inst6|Add1~410 ; cout0 ;
; |v_fpga|counter:inst6|Add1~409 ; |v_fpga|counter:inst6|Add1~410COUT1 ; cout1 ;
; |v_fpga|counter:inst6|Add1~411 ; |v_fpga|counter:inst6|Add1~411 ; combout ;
; |v_fpga|counter:inst6|Add1~413 ; |v_fpga|counter:inst6|Add1~413 ; combout ;
; |v_fpga|counter:inst6|Add1~413 ; |v_fpga|counter:inst6|Add1~414 ; cout0 ;
; |v_fpga|counter:inst6|Add1~413 ; |v_fpga|counter:inst6|Add1~414COUT1 ; cout1 ;
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