v_fpga.fit.smsg

自己写的iic配置芯片的源程序

Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 72 (unused VREF, 3.30 VCCIO, 38 input, 34 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 12 total pin(s) used --  27 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 2 total pin(s) used --  37 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 7 total pin(s) used --  38 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  38 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  44 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "HRCEC" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[10]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[11]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[12]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[13]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[14]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[15]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[16]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[17]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[18]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[19]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[20]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[21]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[22]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[23]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[2]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[3]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[6]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[7]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[8]" is assigned to location or region, but does not exist in design
    Warning: Node "HRQE[9]" is assigned to location or region, but does not exist in design
    Warning: Node "HRRESET" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[10]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[11]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[12]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[13]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[14]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[15]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[16]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[17]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[18]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[19]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[20]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[21]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[22]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[23]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[2]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[3]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[6]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[7]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[8]" is assigned to location or region, but does not exist in design
    Warning: Node "HTD[9]" is assigned to location or region, but does not exist in design
    Warning: Node "HTRESET" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:07
Info: Estimated most critical path is register to register delay of 2.817 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X50_Y28; Fanout = 1; REG Node = 'Init9011:inst1|subadd[7]'
    Info: 2: + IC(0.113 ns) + CELL(0.527 ns) = 0.640 ns; Loc. = LAB_X50_Y28; Fanout = 1; COMB Node = 'Init9011:inst1|Selector160~807'
    Info: 3: + IC(1.024 ns) + CELL(0.381 ns) = 2.045 ns; Loc. = LAB_X51_Y27; Fanout = 1; COMB Node = 'Init9011:inst1|Selector160~810'
    Info: 4: + IC(0.210 ns) + CELL(0.562 ns) = 2.817 ns; Loc. = LAB_X51_Y27; Fanout = 1; REG Node = 'Init9011:inst1|SDAo'
    Info: Total cell delay = 1.470 ns ( 52.18 % )
    Info: Total interconnect delay = 1.347 ns ( 47.82 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X43_Y21 to location X53_Y31
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Following 29 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin VICLK has GND driving its datain port
    Info: Pin HTDE has GND driving its datain port
    Info: Pin HTHSYNC has GND driving its datain port
    Info: Pin HTVSYNC has GND driving its datain port
    Info: Pin FAHSYNC has GND driving its datain port
    Info: Pin FAVSYNC has GND driving its datain port
    Info: Pin HRHPD has GND driving its datain port
    Info: Pin ack1 has GND driving its datain port
    Info: Pin ack2 has GND driving its datain port
    Info: Pin HTD3 has GND driving its datain port
    Info: Pin HTD2 has GND driving its datain port
    Info: Pin HTD23 has GND driving its datain port
    Info: Pin HTD22 has GND driving its datain port
    Info: Pin HTD21 has GND driving its datain port
    Info: Pin HTD20 has GND driving its datain port
    Info: Pin HTD19 has GND driving its datain port
    Info: Pin HTD18 has GND driving its datain port
    Info: Pin HTD17 has GND driving its datain port
    Info: Pin HTD16 has GND driving its datain port
    Info: Pin HTD15 has GND driving its datain port
    Info: Pin HTD14 has GND driving its datain port
    Info: Pin HTD13 has GND driving its datain port
    Info: Pin HTD12 has GND driving its datain port
    Info: Pin HTD11 has GND driving its datain port
    Info: Pin HTD10 has GND driving its datain port
    Info: Pin HTD9 has GND driving its datain port
    Info: Pin HTD8 has GND driving its datain port
    Info: Pin HTD7 has GND driving its datain port
    Info: Pin HTD6 has GND driving its datain port
Info: Following groups of pins have the same output enable
    Info: Following pins have the same output enable: Init9011:inst1|SCLo~en
        Info: Type bidirectional pin DSCL uses the 3.3-V LVTTL I/O standard
    Info: Following pins have the same output enable: Init9011:inst1|SDAo~en
        Info: Type bidirectional pin DSDA uses the 3.3-V LVTTL I/O standard
Info: Quartus II Fitter was successful. 0 errors, 46 warnings
    Info: Allocated 208 megabytes of memory during processing
    Info: Processing ended: Tue May 20 16:42:46 2008
    Info: Elapsed time: 00:00:29