v_fpga.map.qmsg

自己写的iic配置芯片的源程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 20 16:42:07 2008 " "Info: Processing started: Tue May 20 16:42:07 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off v_fpga -c v_fpga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off v_fpga -c v_fpga" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v_transfer2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file v_transfer2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 v_transfer2-art " "Info: Found design unit 1: v_transfer2-art" {  } { { "v_transfer2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer2.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 v_transfer2 " "Info: Found entity 1: v_transfer2" {  } { { "v_transfer2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer2.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v_fpga.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file v_fpga.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 v_fpga " "Info: Found entity 1: v_fpga" {  } { { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v_transfer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file v_transfer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 v_transfer-art " "Info: Found design unit 1: v_transfer-art" {  } { { "v_transfer.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 v_transfer " "Info: Found entity 1: v_transfer" {  } { { "v_transfer.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011.vhd " "Warning: Can't analyze file -- file C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Init9011.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Init9011.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Init9011-structural " "Info: Found design unit 1: Init9011-structural" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Init9011 " "Info: Found entity 1: Init9011" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "v_fpga " "Info: Elaborating entity \"v_fpga\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NOT_ALL_BITS_USED" "" "Warning: Not all bits are used" {  } { { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 8 -40 128 24 "HRQE\[23..6\]" "" } { 24 -8 160 40 "HRQE\[3..2\]" "" } } } }  } 0 0 "Not all bits are used" 0 0}
{ "Warning" "WGDFX_NOT_ALL_BITS_USED" "" "Warning: Not all bits are used" {  } { { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 40 456 632 56 "HTD\[3..2\]" "" } { 24 456 632 40 "HTD\[23..6\]" "" } } } }  } 0 0 "Not all bits are used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "v_transfer v_transfer:inst " "Info: Elaborating entity \"v_transfer\" for hierarchy \"v_transfer:inst\"" {  } { { "v_fpga.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { -16 248 432 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "VICLK v_transfer.vhd(18) " "Warning (10034): Output port \"VICLK\" at v_transfer.vhd(18) has no driver" {  } { { "v_transfer.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer.vhd" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "HRHPD v_transfer.vhd(25) " "Warning (10034): Output port \"HRHPD\" at v_transfer.vhd(25) has no driver" {  } { { "v_transfer.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer.vhd" 25 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Init9011 Init9011:inst1 " "Info: Elaborating entity \"Init9011\" for hierarchy \"Init9011:inst1\"" {  } { { "v_fpga.bdf" "inst1" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 448 584 752 640 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "addwr Init9011.vhd(90) " "Warning (10631): VHDL Process Statement warning at Init9011.vhd(90): inferring latch(es) for signal or variable \"addwr\", which holds its previous value in one or more paths through the process" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "subadd Init9011.vhd(90) " "Warning (10631): VHDL Process Statement warning at Init9011.vhd(90): inferring latch(es) for signal or variable \"subadd\", which holds its previous value in one or more paths through the process" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "subadd2 Init9011.vhd(90) " "Warning (10631): VHDL Process Statement warning at Init9011.vhd(90): inferring latch(es) for signal or variable \"subadd2\", which holds its previous value in one or more paths through the process" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "data Init9011.vhd(90) " "Warning (10631): VHDL Process Statement warning at Init9011.vhd(90): inferring latch(es) for signal or variable \"data\", which holds its previous value in one or more paths through the process" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "ibusy Init9011.vhd(299) " "Warning (10036): Verilog HDL or VHDL warning at Init9011.vhd(299): object \"ibusy\" assigned a value but never read" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 299 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "nxt_state Init9011.vhd(297) " "Warning (10631): VHDL Process Statement warning at Init9011.vhd(297): inferring latch(es) for signal or variable \"nxt_state\", which holds its previous value in one or more paths through the process" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 297 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "done Init9011.vhd(297) " "Warning (10631): VHDL Process Statement warning at Init9011.vhd(297): inferring latch(es) for signal or variable \"done\", which holds its previous value in one or more paths through the process" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 297 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "CFGDONE Init9011.vhd(297) " "Warning (10631): VHDL Process Statement warning at Init9011.vhd(297): inferring latch(es) for signal or variable \"CFGDONE\", which holds its previous value in one or more paths through the process" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 297 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WrDone Init9011.vhd(808) " "Warning (10492): VHDL Process Statement warning at Init9011.vhd(808): signal \"WrDone\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 808 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}