v_fpga.sim.qmsg

自己写的iic配置芯片的源程序

{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[23\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[23\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[22\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[22\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[21\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[21\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[20\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[20\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[19\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[19\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[18\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[18\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[17\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[17\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[16\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[16\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[15\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[15\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[14\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[14\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[13\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[13\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[12\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[12\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[11\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[11\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[10\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[10\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[9\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[9\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[8\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[8\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[7\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[7\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[6\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[6\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[5\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[5\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[4\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[4\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[3\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[3\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[2\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[2\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[1\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[1\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|v_fpga\|HRQE\[0\] " "Warning: Can't find signal in vector source file for input pin \"\|v_fpga\|HRQE\[0\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|v_fpga\|sim_i2c:inst3\|SCLo " "Info: Register: \|v_fpga\|sim_i2c:inst3\|SCLo" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|v_fpga\|sim_i2c:inst3\|SDAo " "Info: Register: \|v_fpga\|sim_i2c:inst3\|SDAo" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     60.90 % " "Info: Simulation coverage is      60.90 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "7073759 " "Info: Number of transitions in simulation is 7073759" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "v_fpga.vwf " "Info: Vector file v_fpga.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 115 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 115 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "95 " "Info: Allocated 95 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 05 21:50:43 2008 " "Info: Processing ended: Mon May 05 21:50:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:24 " "Info: Elapsed time: 00:01:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}