v_fpga.tan.qmsg

自己写的iic配置芯片的源程序

{ "Info" "ITDB_TSU_RESULT" "Init9011:inst1\|SDAo DSDA CLK27 1.758 ns register " "Info: tsu for register \"Init9011:inst1\|SDAo\" (data pin = \"DSDA\", clock pin = \"CLK27\") is 1.758 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.621 ns + Longest pin register " "Info: + Longest pin to register delay is 9.621 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DSDA 1 PIN PIN_G5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G5; Fanout = 1; PIN Node = 'DSDA'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSDA } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 552 784 960 568 "DSDA" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.490 ns) 1.490 ns DSDA~0 2 COMB IOC_X0_Y28_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = IOC_X0_Y28_N0; Fanout = 1; COMB Node = 'DSDA~0'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { DSDA DSDA~0 } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 552 784 960 568 "DSDA" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.539 ns) + CELL(0.100 ns) 7.129 ns Init9011:inst1\|Selector160~808 3 COMB LC_X47_Y28_N8 1 " "Info: 3: + IC(5.539 ns) + CELL(0.100 ns) = 7.129 ns; Loc. = LC_X47_Y28_N8; Fanout = 1; COMB Node = 'Init9011:inst1\|Selector160~808'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.639 ns" { DSDA~0 Init9011:inst1|Selector160~808 } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 831 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.536 ns) + CELL(0.527 ns) 9.192 ns Init9011:inst1\|Selector160~810 4 COMB LC_X51_Y27_N7 1 " "Info: 4: + IC(1.536 ns) + CELL(0.527 ns) = 9.192 ns; Loc. = LC_X51_Y27_N7; Fanout = 1; COMB Node = 'Init9011:inst1\|Selector160~810'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.063 ns" { Init9011:inst1|Selector160~808 Init9011:inst1|Selector160~810 } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 831 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.159 ns) + CELL(0.270 ns) 9.621 ns Init9011:inst1\|SDAo 5 REG LC_X51_Y27_N8 1 " "Info: 5: + IC(0.159 ns) + CELL(0.270 ns) = 9.621 ns; Loc. = LC_X51_Y27_N8; Fanout = 1; REG Node = 'Init9011:inst1\|SDAo'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.429 ns" { Init9011:inst1|Selector160~810 Init9011:inst1|SDAo } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.387 ns ( 24.81 % ) " "Info: Total cell delay = 2.387 ns ( 24.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.234 ns ( 75.19 % ) " "Info: Total interconnect delay = 7.234 ns ( 75.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.621 ns" { DSDA DSDA~0 Init9011:inst1|Selector160~808 Init9011:inst1|Selector160~810 Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.621 ns" { DSDA DSDA~0 Init9011:inst1|Selector160~808 Init9011:inst1|Selector160~810 Init9011:inst1|SDAo } { 0.000ns 0.000ns 5.539ns 1.536ns 0.159ns } { 0.000ns 1.490ns 0.100ns 0.527ns 0.270ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK27 destination 7.874 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK27\" to destination register is 7.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns CLK27 1 CLK PIN_R26 35 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_R26; Fanout = 35; CLK Node = 'CLK27'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK27 } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 360 -48 120 376 "CLK27" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(0.846 ns) 3.815 ns HWReset9011_9034:inst4\|en 2 REG LC_X1_Y17_N1 173 " "Info: 2: + IC(2.094 ns) + CELL(0.846 ns) = 3.815 ns; Loc. = LC_X1_Y17_N1; Fanout = 173; REG Node = 'HWReset9011_9034:inst4\|en'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.940 ns" { CLK27 HWReset9011_9034:inst4|en } "NODE_NAME" } } { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.415 ns) + CELL(0.644 ns) 7.874 ns Init9011:inst1\|SDAo 3 REG LC_X51_Y27_N8 1 " "Info: 3: + IC(3.415 ns) + CELL(0.644 ns) = 7.874 ns; Loc. = LC_X51_Y27_N8; Fanout = 1; REG Node = 'Init9011:inst1\|SDAo'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.059 ns" { HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.365 ns ( 30.04 % ) " "Info: Total cell delay = 2.365 ns ( 30.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.509 ns ( 69.96 % ) " "Info: Total interconnect delay = 5.509 ns ( 69.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } { 0.000ns 0.000ns 2.094ns 3.415ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.621 ns" { DSDA DSDA~0 Init9011:inst1|Selector160~808 Init9011:inst1|Selector160~810 Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.621 ns" { DSDA DSDA~0 Init9011:inst1|Selector160~808 Init9011:inst1|Selector160~810 Init9011:inst1|SDAo } { 0.000ns 0.000ns 5.539ns 1.536ns 0.159ns } { 0.000ns 1.490ns 0.100ns 0.527ns 0.270ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } { 0.000ns 0.000ns 2.094ns 3.415ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK27 DOUT\[3\] Init9011:inst1\|Dout\[3\] 19.206 ns register " "Info: tco from clock \"CLK27\" to destination pin \"DOUT\[3\]\" through register \"Init9011:inst1\|Dout\[3\]\" is 19.206 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK27 source 12.369 ns + Longest register " "Info: + Longest clock path from clock \"CLK27\" to source register is 12.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns CLK27 1 CLK PIN_R26 35 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_R26; Fanout = 35; CLK Node = 'CLK27'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK27 } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 360 -48 120 376 "CLK27" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(0.846 ns) 3.815 ns HWReset9011_9034:inst4\|en 2 REG LC_X1_Y17_N1 173 " "Info: 2: + IC(2.094 ns) + CELL(0.846 ns) = 3.815 ns; Loc. = LC_X1_Y17_N1; Fanout = 173; REG Node = 'HWReset9011_9034:inst4\|en'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.940 ns" { CLK27 HWReset9011_9034:inst4|en } "NODE_NAME" } } { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.642 ns) + CELL(0.846 ns) 8.303 ns Init9011:inst1\|state.stop_c 3 REG LC_X1_Y13_N2 11 " "Info: 3: + IC(3.642 ns) + CELL(0.846 ns) = 8.303 ns; Loc. = LC_X1_Y13_N2; Fanout = 11; REG Node = 'Init9011:inst1\|state.stop_c'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.488 ns" { HWReset9011_9034:inst4|en Init9011:inst1|state.stop_c } "NODE_NAME" } } { "Init9011.vhd" "" { Te