📄 v_fpga.tan.qmsg
字号:
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK27 register Init9011:inst1\|data\[3\] register Init9011:inst1\|SDAo 1.304 ns " "Info: Slack time is 1.304 ns for clock \"CLK27\" between source register \"Init9011:inst1\|data\[3\]\" and destination register \"Init9011:inst1\|SDAo\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "29.04 MHz 34.43 ns " "Info: Fmax is 29.04 MHz (period= 34.43 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.301 ns + Largest register register " "Info: + Largest register to register requirement is 4.301 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "18.519 ns + " "Info: + Setup relationship between source and destination is 18.519 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 37.037 ns " "Info: + Latch edge is 37.037 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK27 37.037 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLK27\" is 37.037 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 18.518 ns " "Info: - Launch edge is 18.518 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK27 37.037 ns 18.518 ns inverted 50 " "Info: Clock period of Source clock \"CLK27\" is 37.037 ns with inverted offset of 18.518 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-14.207 ns + Largest " "Info: + Largest clock skew is -14.207 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK27 destination 7.874 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK27\" to destination register is 7.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns CLK27 1 CLK PIN_R26 35 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_R26; Fanout = 35; CLK Node = 'CLK27'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK27 } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 360 -48 120 376 "CLK27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(0.846 ns) 3.815 ns HWReset9011_9034:inst4\|en 2 REG LC_X1_Y17_N1 173 " "Info: 2: + IC(2.094 ns) + CELL(0.846 ns) = 3.815 ns; Loc. = LC_X1_Y17_N1; Fanout = 173; REG Node = 'HWReset9011_9034:inst4\|en'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.940 ns" { CLK27 HWReset9011_9034:inst4|en } "NODE_NAME" } } { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.415 ns) + CELL(0.644 ns) 7.874 ns Init9011:inst1\|SDAo 3 REG LC_X51_Y27_N8 1 " "Info: 3: + IC(3.415 ns) + CELL(0.644 ns) = 7.874 ns; Loc. = LC_X51_Y27_N8; Fanout = 1; REG Node = 'Init9011:inst1\|SDAo'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.059 ns" { HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.365 ns ( 30.04 % ) " "Info: Total cell delay = 2.365 ns ( 30.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.509 ns ( 69.96 % ) " "Info: Total interconnect delay = 5.509 ns ( 69.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } { 0.000ns 0.000ns 2.094ns 3.415ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK27 source 22.081 ns - Longest register " "Info: - Longest clock path from clock \"CLK27\" to source register is 22.081 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns CLK27 1 CLK PIN_R26 35 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_R26; Fanout = 35; CLK Node = 'CLK27'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK27 } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 360 -48 120 376 "CLK27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(0.846 ns) 3.815 ns HWReset9011_9034:inst4\|en 2 REG LC_X1_Y17_N1 173 " "Info: 2: + IC(2.094 ns) + CELL(0.846 ns) = 3.815 ns; Loc. = LC_X1_Y17_N1; Fanout = 173; REG Node = 'HWReset9011_9034:inst4\|en'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.940 ns" { CLK27 HWReset9011_9034:inst4|en } "NODE_NAME" } } { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.667 ns) + CELL(0.846 ns) 8.328 ns Init9011:inst1\|WrDone 3 REG LC_X1_Y17_N5 28 " "Info: 3: + IC(3.667 ns) + CELL(0.846 ns) = 8.328 ns; Loc. = LC_X1_Y17_N5; Fanout = 28; REG Node = 'Init9011:inst1\|WrDone'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.513 ns" { HWReset9011_9034:inst4|en Init9011:inst1|WrDone } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 792 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.554 ns) + CELL(1.191 ns) 13.073 ns Init9011:inst1\|altsyncram:Mux0_rtl_0\|altsyncram_ibu:auto_generated\|ram_block1a8~porta_address_reg5 4 MEM M4K_X37_Y1 19 " "Info: 4: + IC(3.554 ns) + CELL(1.191 ns) = 13.073 ns; Loc. = M4K_X37_Y1; Fanout = 19; MEM Node = 'Init9011:inst1\|altsyncram:Mux0_rtl_0\|altsyncram_ibu:auto_generated\|ram_block1a8~porta_address_reg5'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.745 ns" { Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_ibu.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/db/altsyncram_ibu.tdf" 187 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.012 ns) 17.085 ns Init9011:inst1\|altsyncram:Mux0_rtl_0\|altsyncram_ibu:auto_generated\|q_a\[1\] 5 MEM M4K_X37_Y1 18 " "Info: 5: + IC(0.000 ns) + CELL(4.012 ns) = 17.085 ns; Loc. = M4K_X37_Y1; Fanout = 18; MEM Node = 'Init9011:inst1\|altsyncram:Mux0_rtl_0\|altsyncram_ibu:auto_generated\|q_a\[1\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.012 ns" { Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_ibu.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/db/altsyncram_ibu.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.896 ns) + CELL(0.100 ns) 22.081 ns Init9011:inst1\|data\[3\] 6 REG LC_X52_Y28_N7 2 " "Info: 6: + IC(4.896 ns) + CELL(0.100 ns) = 22.081 ns; Loc. = LC_X52_Y28_N7; Fanout = 2; REG Node = 'Init9011:inst1\|data\[3\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.996 ns" { Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 90 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.870 ns ( 35.64 % ) " "Info: Total cell delay = 7.870 ns ( 35.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.211 ns ( 64.36 % ) " "Info: Total interconnect delay = 14.211 ns ( 64.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "22.081 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "22.081 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } { 0.000ns 0.000ns 2.094ns 3.667ns 3.554ns 0.000ns 4.896ns } { 0.000ns 0.875ns 0.846ns 0.846ns 1.191ns 4.012ns 0.100ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } { 0.000ns 0.000ns 2.094ns 3.415ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "22.081 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "22.081 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } { 0.000ns 0.000ns 2.094ns 3.667ns 3.554ns 0.000ns 4.896ns } { 0.000ns 0.875ns 0.846ns 0.846ns 1.191ns 4.012ns 0.100ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns - " "Info: - Micro clock to output delay of source is 0.000 ns" { } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 90 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns - " "Info: - Micro setup delay of destination is 0.011 ns" { } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 55 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } { 0.000ns 0.000ns 2.094ns 3.415ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "22.081 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "22.081 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } { 0.000ns 0.000ns 2.094ns 3.667ns 3.554ns 0.000ns 4.896ns } { 0.000ns 0.875ns 0.846ns 0.846ns 1.191ns 4.012ns 0.100ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.997 ns - Longest register register " "Info: - Longest register to register delay is 2.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Init9011:inst1\|data\[3\] 1 REG LC_X52_Y28_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y28_N7; Fanout = 2; REG Node = 'Init9011:inst1\|data\[3\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Init9011:inst1|data[3] } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 90 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.244 ns) 0.673 ns Init9011:inst1\|Selector160~802 2 COMB LC_X52_Y28_N2 1 " "Info: 2: + IC(0.429 ns) + CELL(0.244 ns) = 0.673 ns; Loc. = LC_X52_Y28_N2; Fanout = 1; COMB Node = 'Init9011:inst1\|Selector160~802'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { Init9011:inst1|data[3] Init9011:inst1|Selector160~802 } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 831 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.236 ns) + CELL(0.244 ns) 2.153 ns Init9011:inst1\|Selector160~803 3 COMB LC_X51_Y27_N5 1 " "Info: 3: + IC(1.236 ns) + CELL(0.244 ns) = 2.153 ns; Loc. = LC_X51_Y27_N5; Fanout = 1; COMB Node = 'Init9011:inst1\|Selector160~803'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.480 ns" { Init9011:inst1|Selector160~802 Init9011:inst1|Selector160~803 } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 831 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.418 ns) 2.997 ns Init9011:inst1\|SDAo 4 REG LC_X51_Y27_N8 1 " "Info: 4: + IC(0.426 ns) + CELL(0.418 ns) = 2.997 ns; Loc. = LC_X51_Y27_N8; Fanout = 1; REG Node = 'Init9011:inst1\|SDAo'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.844 ns" { Init9011:inst1|Selector160~803 Init9011:inst1|SDAo } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.906 ns ( 30.23 % ) " "Info: Total cell delay = 0.906 ns ( 30.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.091 ns ( 69.77 % ) " "Info: Total interconnect delay = 2.091 ns ( 69.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.997 ns" { Init9011:inst1|data[3] Init9011:inst1|Selector160~802 Init9011:inst1|Selector160~803 Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.997 ns" { Init9011:inst1|data[3] Init9011:inst1|Selector160~802 Init9011:inst1|Selector160~803 Init9011:inst1|SDAo } { 0.000ns 0.429ns 1.236ns 0.426ns } { 0.000ns 0.244ns 0.244ns 0.418ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|SDAo } { 0.000ns 0.000ns 2.094ns 3.415ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "22.081 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "22.081 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|ram_block1a8~porta_address_reg5 Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated|q_a[1] Init9011:inst1|data[3] } { 0.000ns 0.000ns 2.094ns 3.667ns 3.554ns 0.000ns 4.896ns } { 0.000ns 0.875ns 0.846ns 0.846ns 1.191ns 4.012ns 0.100ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.997 ns" { Init9011:inst1|data[3] Init9011:inst1|Selector160~802 Init9011:inst1|Selector160~803 Init9011:inst1|SDAo } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.997 ns" { Init9011:inst1|data[3] Init9011:inst1|Selector160~802 Init9011:inst1|Selector160~803 Init9011:inst1|SDAo } { 0.000ns 0.429ns 1.236ns 0.426ns } { 0.000ns 0.244ns 0.244ns 0.418ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK27 register HWReset9011_9034:inst4\|HTXRST register Init9011:inst1\|WrDone -802 ps " "Info: Minimum slack time is -802 ps for clock \"CLK27\" between source register \"HWReset9011_9034:inst4\|HTXRST\" and destination register \"Init9011:inst1\|WrDone\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.796 ns + Shortest register register " "Info: + Shortest register to register delay is 3.796 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HWReset9011_9034:inst4\|HTXRST 1 REG LC_X30_Y23_N5 166 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y23_N5; Fanout = 166; REG Node = 'HWReset9011_9034:inst4\|HTXRST'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { HWReset9011_9034:inst4|HTXRST } "NODE_NAME" } } { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.962 ns) + CELL(0.834 ns) 3.796 ns Init9011:inst1\|WrDone 2 REG LC_X1_Y17_N5 28 " "Info: 2: + IC(2.962 ns) + CELL(0.834 ns) = 3.796 ns; Loc. = LC_X1_Y17_N5; Fanout = 28; REG Node = 'Init9011:inst1\|WrDone'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.796 ns" { HWReset9011_9034:inst4|HTXRST Init9011:inst1|WrDone } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 792 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.834 ns ( 21.97 % ) " "Info: Total cell delay = 0.834 ns ( 21.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.962 ns ( 78.03 % ) " "Info: Total interconnect delay = 2.962 ns ( 78.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.796 ns" { HWReset9011_9034:inst4|HTXRST Init9011:inst1|WrDone } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.796 ns" { HWReset9011_9034:inst4|HTXRST Init9011:inst1|WrDone } { 0.000ns 2.962ns } { 0.000ns 0.834ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.598 ns - Smallest register register " "Info: - Smallest register to register requirement is 4.598 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK27 37.037 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLK27\" is 37.037 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK27 37.037 ns 0.000 ns 50 " "Info: Clock period of Source clock \"CLK27\" is 37.037 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.686 ns + Smallest " "Info: + Smallest clock skew is 4.686 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK27 destination 8.126 ns + Longest register " "Info: + Longest clock path from clock \"CLK27\" to destination register is 8.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns CLK27 1 CLK PIN_R26 35 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_R26; Fanout = 35; CLK Node = 'CLK27'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK27 } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 360 -48 120 376 "CLK27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(0.846 ns) 3.815 ns HWReset9011_9034:inst4\|en 2 REG LC_X1_Y17_N1 173 " "Info: 2: + IC(2.094 ns) + CELL(0.846 ns) = 3.815 ns; Loc. = LC_X1_Y17_N1; Fanout = 173; REG Node = 'HWReset9011_9034:inst4\|en'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.940 ns" { CLK27 HWReset9011_9034:inst4|en } "NODE_NAME" } } { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.667 ns) + CELL(0.644 ns) 8.126 ns Init9011:inst1\|WrDone 3 REG LC_X1_Y17_N5 28 " "Info: 3: + IC(3.667 ns) + CELL(0.644 ns) = 8.126 ns; Loc. = LC_X1_Y17_N5; Fanout = 28; REG Node = 'Init9011:inst1\|WrDone'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.311 ns" { HWReset9011_9034:inst4|en Init9011:inst1|WrDone } "NODE_NAME" } } { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 792 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.365 ns ( 29.10 % ) " "Info: Total cell delay = 2.365 ns ( 29.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.761 ns ( 70.90 % ) " "Info: Total interconnect delay = 5.761 ns ( 70.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.126 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.126 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } { 0.000ns 0.000ns 2.094ns 3.667ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK27 source 3.440 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK27\" to source register is 3.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns CLK27 1 CLK PIN_R26 35 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_R26; Fanout = 35; CLK Node = 'CLK27'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK27 } "NODE_NAME" } } { "v_fpga.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf" { { 360 -48 120 376 "CLK27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.921 ns) + CELL(0.644 ns) 3.440 ns HWReset9011_9034:inst4\|HTXRST 2 REG LC_X30_Y23_N5 166 " "Info: 2: + IC(1.921 ns) + CELL(0.644 ns) = 3.440 ns; Loc. = LC_X30_Y23_N5; Fanout = 166; REG Node = 'HWReset9011_9034:inst4\|HTXRST'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.565 ns" { CLK27 HWReset9011_9034:inst4|HTXRST } "NODE_NAME" } } { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns ( 44.16 % ) " "Info: Total cell delay = 1.519 ns ( 44.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.921 ns ( 55.84 % ) " "Info: Total interconnect delay = 1.921 ns ( 55.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.440 ns" { CLK27 HWReset9011_9034:inst4|HTXRST } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.440 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|HTXRST } { 0.000ns 0.000ns 1.921ns } { 0.000ns 0.875ns 0.644ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.126 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.126 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } { 0.000ns 0.000ns 2.094ns 3.667ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.440 ns" { CLK27 HWReset9011_9034:inst4|HTXRST } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.440 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|HTXRST } { 0.000ns 0.000ns 1.921ns } { 0.000ns 0.875ns 0.644ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns - " "Info: - Micro clock to output delay of source is 0.202 ns" { } { { "HWReset9011_9034.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/HWReset9011_9034.vhd" 10 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.114 ns + " "Info: + Micro hold delay of destination is 0.114 ns" { } { { "Init9011.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd" 792 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.126 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.126 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } { 0.000ns 0.000ns 2.094ns 3.667ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.440 ns" { CLK27 HWReset9011_9034:inst4|HTXRST } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.440 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|HTXRST } { 0.000ns 0.000ns 1.921ns } { 0.000ns 0.875ns 0.644ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.796 ns" { HWReset9011_9034:inst4|HTXRST Init9011:inst1|WrDone } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.796 ns" { HWReset9011_9034:inst4|HTXRST Init9011:inst1|WrDone } { 0.000ns 2.962ns } { 0.000ns 0.834ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.126 ns" { CLK27 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.126 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|en Init9011:inst1|WrDone } { 0.000ns 0.000ns 2.094ns 3.667ns } { 0.000ns 0.875ns 0.846ns 0.644ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.440 ns" { CLK27 HWReset9011_9034:inst4|HTXRST } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.440 ns" { CLK27 CLK27~out0 HWReset9011_9034:inst4|HTXRST } { 0.000ns 0.000ns 1.921ns } { 0.000ns 0.875ns 0.644ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "CLK27 1 " "Warning: Can't achieve minimum setup and hold requirement CLK27 along 1 path(s). See Report window for details." { } { } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
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