v_fpga.hier_info

自己写的iic配置芯片的源程序

|v_fpga
VICLK <= v_transfer:inst.VICLK
HRODCK => v_transfer:inst.HRODCK
HRDE => v_transfer:inst.HRDE
MODE => v_transfer:inst.MODE
MODE => v_transfer2:inst2.MODE
HRHSYNC => v_transfer:inst.HRHSYNC
HRVSYNC => v_transfer:inst.HRVSYNC
HRSCDT => v_transfer:inst.HRSCDT
HRINT => v_transfer:inst.HRINT
CLK27 => HWReset9011_9034:inst4.CLKIN
CLK27 => v_transfer2:inst2.VOCLK
DSCL <= Init9011:inst1.SCL
DSDA <= Init9011:inst1.SDA
HRQE23 => v_transfer:inst.HRQE1[23]
HRQE22 => v_transfer:inst.HRQE1[22]
HRQE21 => v_transfer:inst.HRQE1[21]
HRQE20 => v_transfer:inst.HRQE1[20]
HRQE19 => v_transfer:inst.HRQE1[19]
HRQE18 => v_transfer:inst.HRQE1[18]
HRQE17 => v_transfer:inst.HRQE1[17]
HRQE16 => v_transfer:inst.HRQE1[16]
HRQE15 => v_transfer:inst.HRQE1[15]
HRQE14 => v_transfer:inst.HRQE1[14]
HRQE13 => v_transfer:inst.HRQE1[13]
HRQE12 => v_transfer:inst.HRQE1[12]
HRQE11 => v_transfer:inst.HRQE1[11]
HRQE10 => v_transfer:inst.HRQE1[10]
HRQE9 => v_transfer:inst.HRQE1[9]
HRQE8 => v_transfer:inst.HRQE1[8]
HRQE7 => v_transfer:inst.HRQE1[7]
HRQE6 => v_transfer:inst.HRQE1[6]
HRQE3 => v_transfer:inst.HRQE2[3]
HRQE2 => v_transfer:inst.HRQE2[2]
HTIDCK <= v_transfer:inst.HTIDCK
HTDE <= v_transfer:inst.HTDE
HTHSYNC <= v_transfer:inst.HTHSYNC
HTVSYNC <= v_transfer:inst.HTVSYNC
FAHSYNC <= HWReset9011_9034:inst4.FAHSYNC
FAVSYNC <= HWReset9011_9034:inst4.FAVSYNC
HRHPD <= v_transfer:inst.HRHPD
ack1 <= Init9011:inst1.ack1
ack2 <= Init9011:inst1.ack2
test1 <= Init9011:inst1.test1
CLK400K <= HWReset9011_9034:inst4.CLKOUT
HRXRET <= HWReset9011_9034:inst4.HRXRST
HTXRST <= HWReset9011_9034:inst4.HTXRST
DOUT[0] <= Init9011:inst1.Dout[0]
DOUT[1] <= Init9011:inst1.Dout[1]
DOUT[2] <= Init9011:inst1.Dout[2]
DOUT[3] <= Init9011:inst1.Dout[3]
DOUT[4] <= Init9011:inst1.Dout[4]
DOUT[5] <= Init9011:inst1.Dout[5]
DOUT[6] <= Init9011:inst1.Dout[6]
DOUT[7] <= Init9011:inst1.Dout[7]
HTD3 <= v_transfer:inst.HTD2[3]
HTD2 <= v_transfer:inst.HTD2[2]
HTD23 <= v_transfer:inst.HTD1[23]
HTD22 <= v_transfer:inst.HTD1[22]
HTD21 <= v_transfer:inst.HTD1[21]
HTD20 <= v_transfer:inst.HTD1[20]
HTD19 <= v_transfer:inst.HTD1[19]
HTD18 <= v_transfer:inst.HTD1[18]
HTD17 <= v_transfer:inst.HTD1[17]
HTD16 <= v_transfer:inst.HTD1[16]
HTD15 <= v_transfer:inst.HTD1[15]
HTD14 <= v_transfer:inst.HTD1[14]
HTD13 <= v_transfer:inst.HTD1[13]
HTD12 <= v_transfer:inst.HTD1[12]
HTD11 <= v_transfer:inst.HTD1[11]
HTD10 <= v_transfer:inst.HTD1[10]
HTD9 <= v_transfer:inst.HTD1[9]
HTD8 <= v_transfer:inst.HTD1[8]
HTD7 <= v_transfer:inst.HTD1[7]
HTD6 <= v_transfer:inst.HTD1[6]
test3[0] <= Init9011:inst1.test3[0]
test3[1] <= Init9011:inst1.test3[1]
test3[2] <= Init9011:inst1.test3[2]
test3[3] <= Init9011:inst1.test3[3]
test3[4] <= Init9011:inst1.test3[4]
VDTO[0] => v_transfer2:inst2.VDTO[0]
VDTO[1] => v_transfer2:inst2.VDTO[1]
VDTO[2] => v_transfer2:inst2.VDTO[2]
VDTO[3] => v_transfer2:inst2.VDTO[3]
VDTO[4] => v_transfer2:inst2.VDTO[4]
VDTO[5] => v_transfer2:inst2.VDTO[5]
VDTO[6] => v_transfer2:inst2.VDTO[6]
VDTO[7] => v_transfer2:inst2.VDTO[7]
VDTO[8] => v_transfer2:inst2.VDTO[8]
VDTO[9] => v_transfer2:inst2.VDTO[9]
VDTO[10] => v_transfer2:inst2.VDTO[10]
VDTO[11] => v_transfer2:inst2.VDTO[11]
VDTO[12] => v_transfer2:inst2.VDTO[12]
VDTO[13] => v_transfer2:inst2.VDTO[13]
VDTO[14] => v_transfer2:inst2.VDTO[14]
VDTO[15] => v_transfer2:inst2.VDTO[15]


|v_fpga|v_transfer:inst
HRQE1[6] => HTD1[6]~reg0.DATAIN
HRQE1[7] => HTD1[7]~reg0.DATAIN
HRQE1[8] => HTD1[8]~reg0.DATAIN
HRQE1[9] => HTD1[9]~reg0.DATAIN
HRQE1[10] => HTD1[10]~reg0.DATAIN
HRQE1[11] => HTD1[11]~reg0.DATAIN
HRQE1[12] => HTD1[12]~reg0.DATAIN
HRQE1[13] => HTD1[13]~reg0.DATAIN
HRQE1[14] => HTD1[14]~reg0.DATAIN
HRQE1[15] => HTD1[15]~reg0.DATAIN
HRQE1[16] => HTD1[16]~reg0.DATAIN
HRQE1[17] => HTD1[17]~reg0.DATAIN
HRQE1[18] => HTD1[18]~reg0.DATAIN
HRQE1[19] => HTD1[19]~reg0.DATAIN
HRQE1[20] => HTD1[20]~reg0.DATAIN
HRQE1[21] => HTD1[21]~reg0.DATAIN
HRQE1[22] => HTD1[22]~reg0.DATAIN
HRQE1[23] => HTD1[23]~reg0.DATAIN
HRQE2[2] => HTD2[2]~reg0.DATAIN
HRQE2[3] => HTD2[3]~reg0.DATAIN
HRODCK => HTVSYNC~reg0.CLK
HRODCK => HTHSYNC~reg0.CLK
HRODCK => HTDE~reg0.CLK
HRODCK => HTD2[2]~reg0.CLK
HRODCK => HTD2[3]~reg0.CLK
HRODCK => HTD1[6]~reg0.CLK
HRODCK => HTD1[7]~reg0.CLK
HRODCK => HTD1[8]~reg0.CLK
HRODCK => HTD1[9]~reg0.CLK
HRODCK => HTD1[10]~reg0.CLK
HRODCK => HTD1[11]~reg0.CLK
HRODCK => HTD1[12]~reg0.CLK
HRODCK => HTD1[13]~reg0.CLK
HRODCK => HTD1[14]~reg0.CLK
HRODCK => HTD1[15]~reg0.CLK
HRODCK => HTD1[16]~reg0.CLK
HRODCK => HTD1[17]~reg0.CLK
HRODCK => HTD1[18]~reg0.CLK
HRODCK => HTD1[19]~reg0.CLK
HRODCK => HTD1[20]~reg0.CLK
HRODCK => HTD1[21]~reg0.CLK
HRODCK => HTD1[22]~reg0.CLK
HRODCK => HTD1[23]~reg0.CLK
HRODCK => HTIDCK.DATAIN
HRDE => HTDE~reg0.DATAIN
MODE => ~NO_FANOUT~
HRHSYNC => HTHSYNC~reg0.DATAIN
HRVSYNC => HTVSYNC~reg0.DATAIN
HRSCDT => ~NO_FANOUT~
HRINT => ~NO_FANOUT~
CFGDONE => HTVSYNC~reg0.ENA
CFGDONE => HTHSYNC~reg0.ENA
CFGDONE => HTDE~reg0.ENA
CFGDONE => HTD2[2]~reg0.ENA
CFGDONE => HTD2[3]~reg0.ENA
CFGDONE => HTD1[6]~reg0.ENA
CFGDONE => HTD1[7]~reg0.ENA
CFGDONE => HTD1[8]~reg0.ENA
CFGDONE => HTD1[9]~reg0.ENA
CFGDONE => HTD1[10]~reg0.ENA
CFGDONE => HTD1[11]~reg0.ENA
CFGDONE => HTD1[12]~reg0.ENA
CFGDONE => HTD1[13]~reg0.ENA
CFGDONE => HTD1[14]~reg0.ENA
CFGDONE => HTD1[15]~reg0.ENA
CFGDONE => HTD1[16]~reg0.ENA
CFGDONE => HTD1[17]~reg0.ENA
CFGDONE => HTD1[18]~reg0.ENA
CFGDONE => HTD1[19]~reg0.ENA
CFGDONE => HTD1[20]~reg0.ENA
CFGDONE => HTD1[21]~reg0.ENA
CFGDONE => HTD1[22]~reg0.ENA
CFGDONE => HTD1[23]~reg0.ENA
VICLK <= <GND>
HTD1[6] <= HTD1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[7] <= HTD1[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[8] <= HTD1[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[9] <= HTD1[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[10] <= HTD1[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[11] <= HTD1[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[12] <= HTD1[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[13] <= HTD1[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[14] <= HTD1[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[15] <= HTD1[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[16] <= HTD1[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[17] <= HTD1[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[18] <= HTD1[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[19] <= HTD1[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[20] <= HTD1[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[21] <= HTD1[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[22] <= HTD1[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD1[23] <= HTD1[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD2[2] <= HTD2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTD2[3] <= HTD2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTIDCK <= HRODCK.DB_MAX_OUTPUT_PORT_TYPE
HTDE <= HTDE~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTHSYNC <= HTHSYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTVSYNC <= HTVSYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
HRHPD <= <GND>


|v_fpga|Init9011:inst1
clk => SDAo.CLK
clk => SDAo~en.CLK
clk => SCLo.CLK
clk => SCLo~en.CLK
clk => cycle[0].CLK
clk => cycle[1].CLK
clk => cycle[2].CLK
clk => cycle[3].CLK
clk => cycle[4].CLK
clk => cycle[5].CLK
clk => cycle[6].CLK
clk => cycle[7].CLK
clk => cycle[8].CLK
clk => cycle[9].CLK
clk => cycle[10].CLK
clk => cycle[11].CLK
clk => cycle[12].CLK
clk => cycle[13].CLK
clk => cycle[14].CLK
clk => WrDone.CLK
clk => \nxt_state_decoder:vcycle[0].CLK
clk => \nxt_state_decoder:vcycle[1].CLK
clk => \nxt_state_decoder:vcycle[2].CLK
clk => \nxt_state_decoder:vcycle[3].CLK
clk => \nxt_state_decoder:vcycle[4].CLK
clk => \nxt_state_decoder:vcycle[5].CLK
clk => \nxt_state_decoder:vcycle[6].CLK
clk => \nxt_state_decoder:vcycle[7].CLK
clk => \nxt_state_decoder:vcycle[8].CLK
clk => \nxt_state_decoder:vcycle[9].CLK
clk => \nxt_state_decoder:vcycle[10].CLK
clk => \nxt_state_decoder:vcycle[11].CLK
clk => \nxt_state_decoder:vcycle[12].CLK
clk => \nxt_state_decoder:vcycle[13].CLK
clk => \nxt_state_decoder:vcycle[14].CLK
clk => state~0.IN1
ena => ~NO_FANOUT~
nReset => Dout[6]$latch.ACLR
nReset => Dout[5]$latch.ACLR
nReset => Dout[4]$latch.ACLR
nReset => Dout[3]$latch.ACLR
nReset => Dout[2]$latch.ACLR
nReset => Dout[1]$latch.ACLR
nReset => Dout[0]$latch.ACLR
nReset => SCLo.PRESET
nReset => SDAo.PRESET
nReset => Dout[7]$latch.ACLR
nReset => \nxt_state_decoder:vcycle[0].ACLR
nReset => \nxt_state_decoder:vcycle[1].ACLR
nReset => \nxt_state_decoder:vcycle[2].ACLR
nReset => \nxt_state_decoder:vcycle[3].ACLR
nReset => \nxt_state_decoder:vcycle[4].ACLR
nReset => \nxt_state_decoder:vcycle[5].ACLR
nReset => \nxt_state_decoder:vcycle[6].ACLR
nReset => \nxt_state_decoder:vcycle[7].ACLR
nReset => \nxt_state_decoder:vcycle[8].ACLR
nReset => \nxt_state_decoder:vcycle[9].ACLR
nReset => \nxt_state_decoder:vcycle[10].ACLR
nReset => \nxt_state_decoder:vcycle[11].ACLR
nReset => \nxt_state_decoder:vcycle[12].ACLR
nReset => \nxt_state_decoder:vcycle[13].ACLR
nReset => \nxt_state_decoder:vcycle[14].ACLR
nReset => SCLo~en.PRESET
nReset => SDAo~en.PRESET
nReset => WrDone.ENA
nReset => state~1.IN1
clk_cnt[0] => ~NO_FANOUT~
clk_cnt[1] => ~NO_FANOUT~
clk_cnt[2] => ~NO_FANOUT~
clk_cnt[3] => ~NO_FANOUT~
clk_cnt[4] => ~NO_FANOUT~
clk_cnt[5] => ~NO_FANOUT~
clk_cnt[6] => ~NO_FANOUT~
clk_cnt[7] => ~NO_FANOUT~
CFGDONE <= <GND>
Dout[0] <= Dout[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
ack1 <= <GND>
ack2 <= <GND>
SCL <= comb~2
SDA <= comb~0
test1 <= WrDone.DB_MAX_OUTPUT_PORT_TYPE
test3[0] <= i[0].DB_MAX_OUTPUT_PORT_TYPE
test3[1] <= i[1].DB_MAX_OUTPUT_PORT_TYPE
test3[2] <= i[2].DB_MAX_OUTPUT_PORT_TYPE
test3[3] <= i[3].DB_MAX_OUTPUT_PORT_TYPE
test3[4] <= i[4].DB_MAX_OUTPUT_PORT_TYPE


|v_fpga|HWReset9011_9034:inst4
CLKIN => HTXRST~reg0.CLK
CLKIN => HRXRST~reg0.CLK
CLKIN => b[0].CLK
CLKIN => b[1].CLK
CLKIN => b[2].CLK
CLKIN => b[3].CLK
CLKIN => b[4].CLK
CLKIN => b[5].CLK
CLKIN => b[6].CLK
CLKIN => b[7].CLK
CLKIN => b[8].CLK
CLKIN => b[9].CLK
CLKIN => b[10].CLK
CLKIN => b[11].CLK
CLKIN => b[12].CLK
CLKIN => b[13].CLK
CLKIN => b[14].CLK
CLKIN => b[15].CLK
CLKIN => b[16].CLK
CLKIN => b[17].CLK
CLKIN => b[18].CLK
CLKIN => b[19].CLK
CLKIN => b[20].CLK
CLKIN => b[21].CLK
CLKIN => b[22].CLK
CLKIN => b[23].CLK
CLKIN => b[24].CLK
CLKIN => b[25].CLK
CLKIN => b[26].CLK
CLKIN => en.CLK
CLKIN => a[0].CLK
CLKIN => a[1].CLK
CLKIN => a[2].CLK
CLKIN => a[3].CLK
CLKIN => a[4].CLK
CLKIN => a[5].CLK
FAHSYNC <= <GND>
FAVSYNC <= <GND>
CLKOUT <= en.DB_MAX_OUTPUT_PORT_TYPE
HRXRST <= HRXRST~reg0.DB_MAX_OUTPUT_PORT_TYPE
HTXRST <= HTXRST~reg0.DB_MAX_OUTPUT_PORT_TYPE


|v_fpga|v_transfer2:inst2
VDTO[0] => ~NO_FANOUT~
VDTO[1] => ~NO_FANOUT~
VDTO[2] => ~NO_FANOUT~
VDTO[3] => ~NO_FANOUT~
VDTO[4] => ~NO_FANOUT~
VDTO[5] => ~NO_FANOUT~
VDTO[6] => ~NO_FANOUT~
VDTO[7] => ~NO_FANOUT~
VDTO[8] => ~NO_FANOUT~
VDTO[9] => ~NO_FANOUT~
VDTO[10] => ~NO_FANOUT~
VDTO[11] => ~NO_FANOUT~
VDTO[12] => ~NO_FANOUT~
VDTO[13] => ~NO_FANOUT~
VDTO[14] => ~NO_FANOUT~
VDTO[15] => ~NO_FANOUT~
VOCLK => HTIDCK.DATAIN
MODE => ~NO_FANOUT~
HTD[0] <= <GND>
HTD[1] <= <GND>
HTD[2] <= <GND>
HTD[3] <= <GND>
HTD[4] <= <GND>
HTD[5] <= <GND>
HTD[6] <= <GND>
HTD[7] <= <GND>
HTD[8] <= <VCC>
HTD[9] <= <VCC>
HTD[10] <= <VCC>
HTD[11] <= <VCC>
HTD[12] <= <VCC>
HTD[13] <= <VCC>
HTD[14] <= <VCC>
HTD[15] <= <VCC>
HTD[16] <= <GND>
HTD[17] <= <GND>
HTD[18] <= <GND>
HTD[19] <= <GND>
HTD[20] <= <VCC>
HTD[21] <= <VCC>
HTD[22] <= <VCC>
HTD[23] <= <VCC>
HTIDCK <= VOCLK.DB_MAX_OUTPUT_PORT_TYPE
HTDE <= <VCC>
HTHSYNC <= <GND>
HTVSYNC <= <GND>