v_fpga.qsf

自己写的iic配置芯片的源程序

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		v_fpga_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:18  JULY 17, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_R8 -to HTD[2]
set_location_assignment PIN_R7 -to HTD[3]
set_location_assignment PIN_R4 -to HTD[8]
set_location_assignment PIN_R5 -to HTD[7]
set_location_assignment PIN_R6 -to HTD[6]
set_location_assignment PIN_T2 -to HTD[14]
set_location_assignment PIN_T3 -to HTD[13]
set_location_assignment PIN_T4 -to HTD[12]
set_location_assignment PIN_T5 -to HTD[11]
set_location_assignment PIN_T6 -to HTD[10]
set_location_assignment PIN_T7 -to HTD[9]
set_location_assignment PIN_U2 -to HTD[17]
set_location_assignment PIN_U5 -to HTD[16]
set_location_assignment PIN_U6 -to HTD[15]
set_location_assignment PIN_V5 -to HTD[19]
set_location_assignment PIN_V6 -to HTD[18]
set_location_assignment PIN_Y1 -to HTD[21]
set_location_assignment PIN_Y2 -to HTD[20]
set_location_assignment PIN_P6 -to HTHSYNC
set_location_assignment PIN_P7 -to HTVSYNC
set_location_assignment PIN_R9 -to HTDE
set_location_assignment PIN_U1 -to HTIDCK
set_location_assignment PIN_G5 -to DSDA
set_location_assignment PIN_G6 -to DSCL
set_location_assignment PIN_R26 -to CLK27
set_location_assignment PIN_AD1 -to DOUT[0]
set_location_assignment PIN_AC3 -to DOUT[2]
set_location_assignment PIN_AC4 -to DOUT[3]
set_location_assignment PIN_AA5 -to DOUT[4]
set_location_assignment PIN_Y5 -to DOUT[5]
set_location_assignment PIN_D21 -to HRDE
set_location_assignment PIN_E22 -to HRHSYNC
set_location_assignment PIN_E21 -to HRVSYNC
set_location_assignment PIN_B15 -to HRODCK
set_location_assignment PIN_D22 -to HRQE[3]
set_location_assignment PIN_D23 -to HRQE[2]
set_location_assignment PIN_A17 -to HRQE[21]
set_location_assignment PIN_A19 -to HRQE[18]
set_location_assignment PIN_A20 -to HRQE[15]
set_location_assignment PIN_A21 -to HRQE[13]
set_location_assignment PIN_A22 -to HRQE[10]
set_location_assignment PIN_A24 -to HRQE[6]
set_location_assignment PIN_B17 -to HRQE[22]
set_location_assignment PIN_B18 -to HRQE[19]
set_location_assignment PIN_B20 -to HRQE[16]
set_location_assignment PIN_B22 -to HRQE[11]
set_location_assignment PIN_B24 -to HRQE[7]
set_location_assignment PIN_C17 -to HRQE[23]
set_location_assignment PIN_C18 -to HRQE[20]
set_location_assignment PIN_C20 -to HRQE[17]
set_location_assignment PIN_C21 -to HRQE[14]
set_location_assignment PIN_C22 -to HRQE[12]
set_location_assignment PIN_C23 -to HRQE[9]
set_location_assignment PIN_C24 -to HRQE[8]
set_location_assignment PIN_D16 -to HRRESET
set_location_assignment PIN_N7 -to HTRESET
set_location_assignment PIN_G19 -to HRHPD
set_location_assignment PIN_G20 -to HRCEC
set_location_assignment PIN_D18 -to HRINT
set_location_assignment PIN_Y6 -to DOUT[7]
set_location_assignment PIN_AA6 -to DOUT[6]
set_location_assignment PIN_AC2 -to DOUT[1]

# Timing Assignments
# ==================
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON
set_global_assignment -name FMAX_REQUIREMENT "27 MHz"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name FAMILY Stratix
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name TOP_LEVEL_ENTITY v_fpga

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1S10F672C7
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"

# Assembler Assignments
# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_DETECTION OFF
set_global_assignment -name GLITCH_INTERVAL "1 ns"
set_global_assignment -name VECTOR_INPUT_SOURCE v_fpga.vwf

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE v_fpga.stp

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

# ---------------------------------------------------
# start AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0)

	# SignalTap II Assignments
	# ========================

# end AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0)
# -------------------------------------------------

# --------------------
# start ENTITY(v_fpga)

	# Fitter Assignments
	# ==================
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to Iclk

# end ENTITY(v_fpga)
# ------------------

set_global_assignment -name VHDL_FILE v_transfer2.vhd
set_global_assignment -name BDF_FILE v_fpga.bdf
set_global_assignment -name VHDL_FILE v_transfer.vhd
set_global_assignment -name VHDL_FILE HWReset9011.vhd
set_global_assignment -name VHDL_FILE Init9011.vhd
set_location_assignment PIN_AA1 -to HTD[23]
set_location_assignment PIN_AA2 -to HTD[22]