v_fpga.map.eqn

自己写的iic配置芯片的源程序

F1L50 = F1_b[10] $ (!F1L50_carry_eqn);

--F1L51 is counter:inst6|add~609
--operation mode is arithmetic

F1L51 = CARRY(F1_b[10] & (!F1L53));


--F1L52 is counter:inst6|add~612
--operation mode is arithmetic

F1L52_carry_eqn = F1L55;
F1L52 = F1_b[9] $ (F1L52_carry_eqn);

--F1L53 is counter:inst6|add~614
--operation mode is arithmetic

F1L53 = CARRY(!F1L55 # !F1_b[9]);


--F1L54 is counter:inst6|add~617
--operation mode is arithmetic

F1L54_carry_eqn = F1L57;
F1L54 = F1_b[8] $ (!F1L54_carry_eqn);

--F1L55 is counter:inst6|add~619
--operation mode is arithmetic

F1L55 = CARRY(F1_b[8] & (!F1L57));


--F1L56 is counter:inst6|add~622
--operation mode is arithmetic

F1L56_carry_eqn = F1L61;
F1L56 = F1_b[7] $ (F1L56_carry_eqn);

--F1L57 is counter:inst6|add~624
--operation mode is arithmetic

F1L57 = CARRY(!F1L61 # !F1_b[7]);


--F1L58 is counter:inst6|add~627
--operation mode is arithmetic

F1L58_carry_eqn = F1L69;
F1L58 = F1_b[3] $ (F1L58_carry_eqn);

--F1L59 is counter:inst6|add~629
--operation mode is arithmetic

F1L59 = CARRY(!F1L69 # !F1_b[3]);


--F1L60 is counter:inst6|add~632
--operation mode is arithmetic

F1L60_carry_eqn = F1L63;
F1L60 = F1_b[6] $ (!F1L60_carry_eqn);

--F1L61 is counter:inst6|add~634
--operation mode is arithmetic

F1L61 = CARRY(F1_b[6] & (!F1L63));


--F1L62 is counter:inst6|add~637
--operation mode is arithmetic

F1L62_carry_eqn = F1L65;
F1L62 = F1_b[5] $ (F1L62_carry_eqn);

--F1L63 is counter:inst6|add~639
--operation mode is arithmetic

F1L63 = CARRY(!F1L65 # !F1_b[5]);


--F1L64 is counter:inst6|add~642
--operation mode is arithmetic

F1L64_carry_eqn = F1L59;
F1L64 = F1_b[4] $ (!F1L64_carry_eqn);

--F1L65 is counter:inst6|add~644
--operation mode is arithmetic

F1L65 = CARRY(F1_b[4] & (!F1L59));


--F1L66 is counter:inst6|add~647
--operation mode is arithmetic

F1L66_carry_eqn = F1L71;
F1L66 = F1_b[1] $ (F1L66_carry_eqn);

--F1L67 is counter:inst6|add~649
--operation mode is arithmetic

F1L67 = CARRY(!F1L71 # !F1_b[1]);


--F1L68 is counter:inst6|add~652
--operation mode is arithmetic

F1L68_carry_eqn = F1L67;
F1L68 = F1_b[2] $ (!F1L68_carry_eqn);

--F1L69 is counter:inst6|add~654
--operation mode is arithmetic

F1L69 = CARRY(F1_b[2] & (!F1L67));


--F1L70 is counter:inst6|add~657
--operation mode is arithmetic

F1L70 = !F1_b[0];

--F1L71 is counter:inst6|add~659
--operation mode is arithmetic

F1L71 = CARRY(F1_b[0]);


--E1_state.ack3_d is sim_i2c:inst3|state.ack3_d
--operation mode is normal

E1_state.ack3_d_lut_out = E1_state.ack3_c;
E1_state.ack3_d = DFFEAS(E1_state.ack3_d_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1L84 is sim_i2c:inst3|done~8
--operation mode is normal

E1L84 = !E1_state.stop_a & !E1_state.stop_b;


--E1L109 is sim_i2c:inst3|reduce_or~450
--operation mode is normal

E1L109 = E1_state.stop_a # E1_state.stop_b # !E1_state.idle;


--E1_\nxt_state_decoder:vi[4] is sim_i2c:inst3|\nxt_state_decoder:vi[4]
--operation mode is normal

E1_\nxt_state_decoder:vi[4]_lut_out = E1_i[4];
E1_\nxt_state_decoder:vi[4] = DFFEAS(E1_\nxt_state_decoder:vi[4]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vi[3] is sim_i2c:inst3|\nxt_state_decoder:vi[3]
--operation mode is normal

E1_\nxt_state_decoder:vi[3]_lut_out = E1_i[3];
E1_\nxt_state_decoder:vi[3] = DFFEAS(E1_\nxt_state_decoder:vi[3]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vi[2] is sim_i2c:inst3|\nxt_state_decoder:vi[2]
--operation mode is normal

E1_\nxt_state_decoder:vi[2]_lut_out = E1_i[2];
E1_\nxt_state_decoder:vi[2] = DFFEAS(E1_\nxt_state_decoder:vi[2]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vi[1] is sim_i2c:inst3|\nxt_state_decoder:vi[1]
--operation mode is normal

E1_\nxt_state_decoder:vi[1]_lut_out = E1_i[1];
E1_\nxt_state_decoder:vi[1] = DFFEAS(E1_\nxt_state_decoder:vi[1]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1L101 is sim_i2c:inst3|LessThan~65
--operation mode is normal

E1L101 = E1_\nxt_state_decoder:vi[4] & (E1_\nxt_state_decoder:vi[3] # E1_\nxt_state_decoder:vi[2] & E1_\nxt_state_decoder:vi[1]);


--E1_\nxt_state_decoder:vcycle[14] is sim_i2c:inst3|\nxt_state_decoder:vcycle[14]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[14]_lut_out = E1_cycle[14];
E1_\nxt_state_decoder:vcycle[14] = DFFEAS(E1_\nxt_state_decoder:vcycle[14]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[13] is sim_i2c:inst3|\nxt_state_decoder:vcycle[13]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[13]_lut_out = E1_cycle[13];
E1_\nxt_state_decoder:vcycle[13] = DFFEAS(E1_\nxt_state_decoder:vcycle[13]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[12] is sim_i2c:inst3|\nxt_state_decoder:vcycle[12]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[12]_lut_out = E1_cycle[12];
E1_\nxt_state_decoder:vcycle[12] = DFFEAS(E1_\nxt_state_decoder:vcycle[12]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[11] is sim_i2c:inst3|\nxt_state_decoder:vcycle[11]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[11]_lut_out = E1_cycle[11];
E1_\nxt_state_decoder:vcycle[11] = DFFEAS(E1_\nxt_state_decoder:vcycle[11]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1L103 is sim_i2c:inst3|nxt_state~123
--operation mode is normal

E1L103 = E1_\nxt_state_decoder:vcycle[14] # E1_\nxt_state_decoder:vcycle[13] # E1_\nxt_state_decoder:vcycle[12] # E1_\nxt_state_decoder:vcycle[11];


--E1_\nxt_state_decoder:vcycle[10] is sim_i2c:inst3|\nxt_state_decoder:vcycle[10]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[10]_lut_out = E1_cycle[10];
E1_\nxt_state_decoder:vcycle[10] = DFFEAS(E1_\nxt_state_decoder:vcycle[10]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[9] is sim_i2c:inst3|\nxt_state_decoder:vcycle[9]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[9]_lut_out = E1_cycle[9];
E1_\nxt_state_decoder:vcycle[9] = DFFEAS(E1_\nxt_state_decoder:vcycle[9]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[8] is sim_i2c:inst3|\nxt_state_decoder:vcycle[8]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[8]_lut_out = E1_cycle[8];
E1_\nxt_state_decoder:vcycle[8] = DFFEAS(E1_\nxt_state_decoder:vcycle[8]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[7] is sim_i2c:inst3|\nxt_state_decoder:vcycle[7]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[7]_lut_out = E1_cycle[7];
E1_\nxt_state_decoder:vcycle[7] = DFFEAS(E1_\nxt_state_decoder:vcycle[7]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1L104 is sim_i2c:inst3|nxt_state~124
--operation mode is normal

E1L104 = E1_\nxt_state_decoder:vcycle[10] # E1_\nxt_state_decoder:vcycle[9] # E1_\nxt_state_decoder:vcycle[8] # E1_\nxt_state_decoder:vcycle[7];


--E1_\nxt_state_decoder:vcycle[6] is sim_i2c:inst3|\nxt_state_decoder:vcycle[6]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[6]_lut_out = E1_cycle[6];
E1_\nxt_state_decoder:vcycle[6] = DFFEAS(E1_\nxt_state_decoder:vcycle[6]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[5] is sim_i2c:inst3|\nxt_state_decoder:vcycle[5]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[5]_lut_out = E1_cycle[5];
E1_\nxt_state_decoder:vcycle[5] = DFFEAS(E1_\nxt_state_decoder:vcycle[5]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[4] is sim_i2c:inst3|\nxt_state_decoder:vcycle[4]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[4]_lut_out = E1_cycle[4];
E1_\nxt_state_decoder:vcycle[4] = DFFEAS(E1_\nxt_state_decoder:vcycle[4]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[3] is sim_i2c:inst3|\nxt_state_decoder:vcycle[3]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[3]_lut_out = E1_cycle[3];
E1_\nxt_state_decoder:vcycle[3] = DFFEAS(E1_\nxt_state_decoder:vcycle[3]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1L105 is sim_i2c:inst3|nxt_state~125
--operation mode is normal

E1L105 = E1_\nxt_state_decoder:vcycle[6] # E1_\nxt_state_decoder:vcycle[5] # E1_\nxt_state_decoder:vcycle[4] # !E1_\nxt_state_decoder:vcycle[3];


--E1L106 is sim_i2c:inst3|nxt_state~126
--operation mode is normal

E1L106 = E1L101 # E1L103 # E1L104 # E1L105;


--E1_\nxt_state_decoder:vcycle[2] is sim_i2c:inst3|\nxt_state_decoder:vcycle[2]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[2]_lut_out = E1_cycle[2];
E1_\nxt_state_decoder:vcycle[2] = DFFEAS(E1_\nxt_state_decoder:vcycle[2]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[0] is sim_i2c:inst3|\nxt_state_decoder:vcycle[0]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[0]_lut_out = E1_cycle[0];
E1_\nxt_state_decoder:vcycle[0] = DFFEAS(E1_\nxt_state_decoder:vcycle[0]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1_\nxt_state_decoder:vcycle[1] is sim_i2c:inst3|\nxt_state_decoder:vcycle[1]
--operation mode is normal

E1_\nxt_state_decoder:vcycle[1]_lut_out = E1_cycle[1];
E1_\nxt_state_decoder:vcycle[1] = DFFEAS(E1_\nxt_state_decoder:vcycle[1]_lut_out, F1_en, F1_HRRESET, , , , , , );


--E1L107 is sim_i2c:inst3|nxt_state~127
--operation mode is normal

E1L107 = E1L106 # E1_\nxt_state_decoder:vcycle[2] # E1_\nxt_state_decoder:vcycle[0] # !E1_\nxt_state_decoder:vcycle[1];


--HB1_q_a[10] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[10]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[10]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = E1_WrDone;
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[10] = HB1_q_a[10]_PORT_A_data_out[0];


--HB1_q_a[0] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[0]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[0]_PORT_A_address_reg = DFFE(HB1_q_a[0]_PORT_A_address, HB1_q_a[0]_clock_0, , , );
HB1_q_a[0]_clock_0 = E1_WrDone;
HB1_q_a[0]_PORT_A_data_out = MEMORY(, , HB1_q_a[0]_PORT_A_address_reg, , , , , , HB1_q_a[0]_clock_0, , , , , );
HB1_q_a[0] = HB1_q_a[0]_PORT_A_data_out[0];


--HB1_q_a[11] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[11]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[11]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[11]_PORT_A_address_reg = DFFE(HB1_q_a[11]_PORT_A_address, HB1_q_a[11]_clock_0, , , );
HB1_q_a[11]_clock_0 = E1_WrDone;
HB1_q_a[11]_PORT_A_data_out = MEMORY(, , HB1_q_a[11]_PORT_A_address_reg, , , , , , HB1_q_a[11]_clock_0, , , , , );
HB1_q_a[11] = HB1_q_a[11]_PORT_A_data_out[0];


--HB1_q_a[12] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[12]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[12]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[12]_PORT_A_address_reg = DFFE(HB1_q_a[12]_PORT_A_address, HB1_q_a[12]_clock_0, , , );
HB1_q_a[12]_clock_0 = E1_WrDone;
HB1_q_a[12]_PORT_A_data_out = MEMORY(, , HB1_q_a[12]_PORT_A_address_reg, , , , , , HB1_q_a[12]_clock_0, , , , , );
HB1_q_a[12] = HB1_q_a[12]_PORT_A_data_out[0];


--HB1_q_a[13] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[13]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[13]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[13]_PORT_A_address_reg = DFFE(HB1_q_a[13]_PORT_A_address, HB1_q_a[13]_clock_0, , , );
HB1_q_a[13]_clock_0 = E1_WrDone;
HB1_q_a[13]_PORT_A_data_out = MEMORY(, , HB1_q_a[13]_PORT_A_address_reg, , , , , , HB1_q_a[13]_clock_0, , , , , );
HB1_q_a[13] = HB1_q_a[13]_PORT_A_data_out[0];


--HB1_q_a[14] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[14]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[14]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[14]_PORT_A_address_reg = DFFE(HB1_q_a[14]_PORT_A_address, HB1_q_a[14]_clock_0, , , );
HB1_q_a[14]_clock_0 = E1_WrDone;
HB1_q_a[14]_PORT_A_data_out = MEMORY(, , HB1_q_a[14]_PORT_A_address_reg, , , , , , HB1_q_a[14]_clock_0, , , , , );
HB1_q_a[14] = HB1_q_a[14]_PORT_A_data_out[0];


--HB1_q_a[15] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[15]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[15]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[15]_PORT_A_address_reg = DFFE(HB1_q_a[15]_PORT_A_address, HB1_q_a[15]_clock_0, , , );
HB1_q_a[15]_clock_0 = E1_WrDone;
HB1_q_a[15]_PORT_A_data_out = MEMORY(, , HB1_q_a[15]_PORT_A_address_reg, , , , , , HB1_q_a[15]_clock_0, , , , , );
HB1_q_a[15] = HB1_q_a[15]_PORT_A_data_out[0];


--HB1_q_a[17] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[17]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[17]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[17]_PORT_A_address_reg = DFFE(HB1_q_a[17]_PORT_A_address, HB1_q_a[17]_clock_0, , , );
HB1_q_a[17]_clock_0 = E1_WrDone;
HB1_q_a[17]_PORT_A_data_out = MEMORY(, , HB1_q_a[17]_PORT_A_address_reg, , , , , , HB1_q_a[17]_clock_0, , , , , );
HB1_q_a[17] = HB1_q_a[17]_PORT_A_data_out[0];


--HB1_q_a[16] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[16]
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[16]_PORT_A_address = BUS(E1L96, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[16]_PORT_A_address_reg = DFFE(HB1_q_a[16]_PORT_A_address, HB1_q_a[16]_clock_0, , , );
HB1_q_a[16]_clock_0 = E1_WrDone;
HB1_q_a[16]_PORT_A_data_out = MEMORY(, , HB1_q_a[16]_PORT_A_address_reg, , , , , , HB1_q_a[16]_clock_0, , , , , );
HB1_q_a[16] = HB1_q_a[16]_PORT_A_data_out[0];


--JB6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

JB6_Q[0] = AMPP_FUNCTION(!A1L7, altera_internal_jtag, G1_CLRN_SIGNAL, G1L16);


--LB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
--operation mode is normal

LB1_state[4] = AMPP_FUNCTION(!A1L7, LB1_state[7], LB1_state[3], LB1_state[4], VCC, !A1L9);


--LB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
--operation mode is normal

LB1_state[3] = AMPP_FUNCTION(!A1L7, A1L9, LB1_state[2], VCC);


--G1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal

G1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L7, P5_dffs[1], A1L108, A1L109, P5_dffs[0], LB1_state[0], LB1_state[12]);


--LB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]
--operation mode is normal

LB1_state[8] = AMPP_FUNCTION(!A1L7, LB1_state[7], LB1_state[5], VCC, A1L9);


--B1_bypass_reg_out is sld_signaltap:auto_signaltap_0|bypass_reg_out
--operation mode is normal

B1_bypass_reg_out = AMPP_FUNCTION(!A1L7, B1_bypass_reg_out, G1L27, altera_internal_jtag, !B1_reset_all);