init9011.vhd

自己写的iic配置芯片的源程序

				isda := subadd(4);

			when wr12_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(4);

			when wr12_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(4);

			when wr12_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(4);
-----------------------------------
            when wr13_a =>            -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd(3);

			when wr13_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(3);

			when wr13_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(3);

			when wr13_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(3);
-----------------------------------
            when wr14_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd(2);

			when wr14_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(2);

			when wr14_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(2);

			when wr14_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(2);
-----------------------------------
            when wr15_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd(1);

			when wr15_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(1);

			when wr15_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(1);

			when wr15_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(1);
-----------------------------------
            when wr16_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd(0);

			when wr16_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(0);

			when wr16_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(0);

			when wr16_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(0);
-----------------------------------
            when ack2_a  =>     -------------------ack
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
			    isda := 'Z';
			when ack2_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
			    isda := 'Z';
			when ack2_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
			    isda := 'Z';
			when ack2_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := 'Z';
---------写低字节地址---------------------------------------------------------------------
            when wr25_a =>            
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(7);

			when wr25_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(7);

			when wr25_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(7);
				ack1<='0';

			when wr25_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(7);
-----------------------------------
            when wr26_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(6);

			when wr26_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(6);

			when wr26_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(6);

			when wr26_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(6);
-----------------------------------
            when wr27_a =>           
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(5);

			when wr27_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(5);

			when wr27_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(5);

			when wr27_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(5);
-----------------------------------
            when wr28_a =>            
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(4);

			when wr28_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(4);

			when wr28_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(4);

			when wr28_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(4);
-----------------------------------
            when wr29_a =>            -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(3);

			when wr29_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(3);

			when wr29_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(3);

			when wr29_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(3);
-----------------------------------
            when wr30_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(2);

			when wr30_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(2);

			when wr30_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(2);

			when wr30_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(2);
-----------------------------------
            when wr31_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(1);

			when wr31_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(1);

			when wr31_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(1);

			when wr31_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(1);
-----------------------------------
            when wr32_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd2(0);

			when wr32_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd2(0);

			when wr32_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd2(0);

			when wr32_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd2(0);
--接收低字节地址响应位---------------------------------
            when ack4_a  =>     
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
			    isda := 'Z';
			when ack4_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
			    isda := 'Z';
			when ack4_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
                iack4:=SDA;
			    isda := 'Z';
			when ack4_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := 'Z';
---------写数据----------------------------------------------------------------------------
            when wr17_a =>            -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(7);

			when wr17_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(7);

			when wr17_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(7);
				ack1<='0';

			when wr17_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(7);
-----------------------------------
            when wr18_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(6);

			when wr18_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(6);

			when wr18_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(6);

			when wr18_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(6);
-----------------------------------
            when wr19_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(5);

			when wr19_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(5);

			when wr19_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(5);

			when wr19_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(5);
-----------------------------------
            when wr20_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(4);

			when wr20_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(4);

			when wr20_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(4);

			when wr20_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(4);
-----------------------------------
            when wr21_a =>            -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(3);

			when wr21_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(3);

			when wr21_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(3);

			when wr21_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(3);
-----------------------------------
            when wr22_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(2);

			when wr22_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(2);

			when wr22_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(2);

			when wr22_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(2);
-----------------------------------
            when wr23_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(1);

			when wr23_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(1);

			when wr23_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(1);

			when wr23_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(1);
-----------------------------------
            when wr24_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := data(0);

			when wr24_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := data(0);

			when wr24_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := data(0);

			when wr24_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := data(0);
-----------------------------------
            when ack3_a  =>     -------------------ack
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
			    isda := 'Z';
			when ack3_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
			    isda := 'Z';
			when ack3_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
                iack3:=SDA;
			    isda := 'Z';
			when ack3_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := 'Z';
-----------------------------------------------------------------------------------------			
			-- stop
			when stop_a =>
				iscl := '0'; -- keep SCL disabled
				isda := '0'; -- set SDA low
			when stop_b =>
				iscl := '1'; -- set SCL high
				isda := '0'; -- keep SDA low
			when stop_c =>
				iscl := '1'; -- keep SCL high
				isda := '1'; -- set SDA high
				Dout(7 downto 0)<= data(7 downto 0);
			when TriState =>
			    iscl := 'Z'; -- set SCL TriState
				isda := 'Z'; -- set SDA TriState
		    WHEN OTHERS =>NULL;
		end case;

		-- generate registers
		if (nReset = '0') then
			SCLo <= '1';
			SDAo <= '1';
			Dout <= "00000000";
			ack1<='0';
			ack2<='0';
		elsif (clk'event and clk = '1') then
			
				SCLo <= iscl;
				SDAo <= isda;
--				ack1 <= iack1;
			    ack2 <= iack2;
		end if;
	end process output_decoder;

	SCL <= '0' when (SCLo = '0') else '1'; -- since SCL is externally pulled-up convert a '1' to a 'Z'(tri-state)
	SDA <= '0' when (SDAo = '0') else '1'; -- since SDA is externally pulled-up convert a '1' to a 'Z'(tri-state)

end architecture structural;

--
--
-- I2C Core
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start:	SCL	~~~~~~~~~~\____
--	SDA	~~~~~~~~\______
--		 x | A | B | C | D | i
--
-- repstart	SCL	____/~~~~\___
--	SDA	__/~~~\______
--		 x | A | B | C | D | i
--
-- stop	SCL	____/~~~~~~~~
--	SDA	==\____/~~~~~
--		 x | A | B | C | D | i
--
--- write	SCL	____/~~~~\____
--	SDA	==X=========X=
--		 x | A | B | C | D | i
--
--- read	SCL	____/~~~~\____
--	SDA	XXXX=====XXXX
--		 x | A | B | C | D | i
--

-- Timing:		Normal mode	Fast mode
-----------------------------------------------------------------
-- Fscl		100KHz		400KHz
-- Th_scl		4.0us		0.6us	High period of SCL
-- Tl_scl		4.7us		1.3us	Low period of SCL
-- Tsu:sta		4.7us		0.6us	setup time for a repeated start condition
-- Tsu:sto		4.0us		0.6us	setup time for a stop conditon
-- Tbuf		4.7us		1.3us	Bus free time between a stop and start condition