init9011.vhd

自己写的iic配置芯片的源程序

--写eeprom时要再加几个状态机，再写一个字节。还要读取一个响应位。
--写9011/9034时要去掉以下写一字节的状态机
            when wr25_a =>
				nxt_state := wr25_b;

			when wr25_b =>
				nxt_state := wr25_c;

			when wr25_c =>
				nxt_state := wr25_d;

			when wr25_d =>
				nxt_state := wr26_a;	
	---------------------------------			
			when wr26_a =>
				nxt_state := wr26_b;

			when wr26_b =>
				nxt_state := wr26_c;

			when wr26_c =>
				nxt_state := wr26_d;

			when wr26_d =>
				nxt_state := wr27_a;
	--------------------------	
	       when wr27_a =>
				nxt_state := wr27_b;

			when wr27_b =>
				nxt_state := wr27_c;

			when wr27_c =>
				nxt_state := wr27_d;

			when wr27_d =>
				nxt_state := wr28_a;
   --------------------------
           when wr28_a =>
				nxt_state := wr28_b;

			when wr28_b =>
				nxt_state := wr28_c;

			when wr28_c =>
				nxt_state := wr28_d;

			when wr28_d =>
				nxt_state := wr29_a;
				-------------
			when wr29_a =>
				nxt_state := wr29_b;

			when wr29_b =>
				nxt_state := wr29_c;

			when wr29_c =>
				nxt_state := wr29_d;

			when wr29_d =>
				nxt_state := wr30_a;
				---------
			when wr30_a =>
				nxt_state := wr30_b;

			when wr30_b =>
				nxt_state := wr30_c;

			when wr30_c =>
				nxt_state := wr30_d;

			when wr30_d =>
				nxt_state := wr31_a;	
				------------
			when wr31_a =>
				nxt_state := wr31_b;

			when wr31_b =>
				nxt_state := wr31_c;

			when wr31_c =>
				nxt_state := wr31_d;

			when wr31_d =>
				nxt_state := wr32_a;
				-----------
		    when wr32_a =>
				nxt_state := wr32_b;

			when wr32_b =>
				nxt_state := wr32_c;

			when wr32_c =>
				nxt_state := wr32_d;

			when wr32_d =>
				nxt_state := ack4_a;	
-----------------接收低字节地址的响应位---------------------------------------------------------------
			when ack4_a =>
				nxt_state := ack4_b;

			when ack4_b=>
				nxt_state := ack4_c;

			when ack4_c =>
				nxt_state := ack4_d;

			when ack4_d =>
				nxt_state := wr17_a; 

---------------------------------------写数据---------------------------------------------------------
			when wr17_a =>
				nxt_state := wr17_b;

			when wr17_b =>
				nxt_state := wr17_c;

			when wr17_c =>
				nxt_state := wr17_d;

			when wr17_d =>
				nxt_state := wr18_a;	
	---------------------------------			
			when wr18_a =>
				nxt_state := wr18_b;

			when wr18_b =>
				nxt_state := wr18_c;

			when wr18_c =>
				nxt_state := wr18_d;

			when wr18_d =>
				nxt_state := wr19_a;
	--------------------------	
	       when wr19_a =>
				nxt_state := wr19_b;

			when wr19_b =>
				nxt_state := wr19_c;

			when wr19_c =>
				nxt_state := wr19_d;

			when wr19_d =>
				nxt_state := wr20_a;
   --------------------------
           when wr20_a =>
				nxt_state := wr20_b;

			when wr20_b =>
				nxt_state := wr20_c;

			when wr20_c =>
				nxt_state := wr20_d;

			when wr20_d =>
				nxt_state := wr21_a;
				-------------
			when wr21_a =>
				nxt_state := wr21_b;

			when wr21_b =>
				nxt_state := wr21_c;

			when wr21_c =>
				nxt_state := wr21_d;

			when wr21_d =>
				nxt_state := wr22_a;
				---------
			when wr22_a =>
				nxt_state := wr22_b;

			when wr22_b =>
				nxt_state := wr22_c;

			when wr22_c =>
				nxt_state := wr22_d;

			when wr22_d =>
				nxt_state := wr23_a;	
				------------
			when wr23_a =>
				nxt_state := wr23_b;

			when wr23_b =>
				nxt_state := wr23_c;

			when wr23_c =>
				nxt_state := wr23_d;

			when wr23_d =>
				nxt_state := wr24_a;
				-----------
		    when wr24_a =>
				nxt_state := wr24_b;

			when wr24_b =>
				nxt_state := wr24_c;

			when wr24_c =>
				nxt_state := wr24_d;

			when wr24_d =>
				nxt_state := ack3_a;	
				-------------------------				
		    when ack3_a =>
				nxt_state := ack3_b;

			when ack3_b=>
				nxt_state := ack3_c;

			when ack3_c =>
				nxt_state := ack3_d;

			when ack3_d =>
				nxt_state := stop_a;	

----------------------------------------------------------------------------------------------------------
			-- stop
			when stop_a =>
				nxt_state := stop_b;
                done := '1';
			when stop_b =>
				nxt_state := stop_c;
                done := '1';
			when stop_c =>
               if vi >= 40 then        --这个数是写的字节数/每次修改写字节都需要修改。
                   nxt_state := TriState;
                   CFGDONE   <= '1';
               else 
                   CFGDONE   <= '0';
                      if vcycle = 10 then 
                         nxt_state := idle;
				      else     --cycle为等待时间周期数信号
				         nxt_state := stop_c;
				      end if;
				end if;
	        when OTHERS => NULL;
		end case;

		-- generate regs
		if (nReset = '0') then
			state <= idle;
		    vi := 0;
		    vcycle := 0;
		elsif (clk'event and clk = '1') then
			state <= nxt_state;
			vcycle := cycle;
			WrDone <= done;
			vi := i;
		end if;
	end process nxt_state_decoder;
----------------------------------------------------------------------------------------------------
	--等待时间，写完一个字节等待一段时间，对时钟进行计数。
	--
	waittime:process(clk)
	begin
	   if clk'event and clk = '1' and WrDone = '1' then 
	      if cycle = 10 then
	         cycle <= 0;
	      else 
	         cycle <= cycle +1;
	      end if;
	    end if;
	end process;
---------------------------------------------------------------------------------------------------
	--纪录正在写第几个字节，直到所需字节全部写完
	--写完一个以后加1
	ByteNum:process(WrDone)
    begin
       if WrDone'event and WrDone = '1' then
              i <= i + 1;
       end if;
    end process;
------------------------------------------------------------------------------------------------------
	-- convert states to SCL and SDA signals
	--
	output_decoder: process (clk, nReset, state)
		variable iscl, isda,iack1,iack2, iack3,iack4: std_logic;
	begin
		case (state) is
			when idle =>
				iscl := SCLo; -- keep SCL in same state
				isda := SDA; -- keep SDA in same state

			-- start
			when start_a =>
				iscl := SCLo; -- keep SCL in same state (for repeated start)
				isda := '1'; -- set SDA high

			when start_b =>
				iscl := '1';	-- set SCL high
				isda := '1'; -- keep SDA high

			when start_c =>
				iscl := '1';	-- keep SCL high
				isda := '0'; -- sel SDA low

			when start_d =>
				iscl := '0'; -- set SCL low
				isda := '0'; -- keep SDA low 

			
-----------------------------------  11101001 11111011
			-- write     first byte is adress 0x60(0110 0000)(1100 0001)
			when wr1_a =>              -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(7);

			when wr1_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(7);

			when wr1_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(7);

			when wr1_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(7);
		------------------------		
		    when wr2_a =>        -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(6);

			when wr2_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(6);

			when wr2_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(6);

			when wr2_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(6);
		--------------------------
		    when wr3_a =>        -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(5);

			when wr3_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(5);

			when wr3_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(5);

			when wr3_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(5);
-----------------------------------
            when wr4_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(4);

			when wr4_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(4);

			when wr4_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(4);

			when wr4_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(4);
-----------------------------------
            when wr5_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(3);

			when wr5_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(3);

			when wr5_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(3);

			when wr5_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(3);
-----------------------------------
            when wr6_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(2);

			when wr6_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(2);

			when wr6_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(2);

			when wr6_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(2);
-----------------------------------
            when wr7_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(1);

			when wr7_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(1);

			when wr7_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(1);

			when wr7_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(1);
-----------------------------------
            when wr8_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := addwr(0);

			when wr8_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := addwr(0);

			when wr8_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := addwr(0);

			when wr8_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := addwr(0);
--------------------------------
            when ack1_a =>       -------------------ack
				iscl := '0';	-- keep SCL low
				isda := 'Z'; 
			--sda := '1';
			when ack1_b =>
				iscl := '1';	-- set SCL high
				isda := 'Z'; 
			--sda := '1';
			when ack1_c =>
				iscl := '1';	-- keep SCL high
				isda := 'Z'; 
			when ack1_d =>
				iscl := '0'; -- set SCL low
				isda := 'Z';
			--	isda := '1';
				
--写高字节地址---------------------------------
            when wr9_a =>            -------------------1
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd(7);

			when wr9_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(7);

			when wr9_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(7);
				ack1<='0';

			when wr9_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(7);
-----------------------------------
            when wr10_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd(6);

			when wr10_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(6);

			when wr10_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(6);

			when wr10_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(6);
-----------------------------------
            when wr11_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA
				isda := subadd(5);

			when wr11_b =>
				iscl := '1';	-- set SCL high
--				isda := txd; -- set SDA
				isda := subadd(5);

			when wr11_c =>
				iscl := '1';	-- keep SCL high
--				isda := txd; -- set SDA
				isda := subadd(5);

			when wr11_d =>
				iscl := '0'; -- set SCL low
--				isda := txd; -- set SDA
				isda := subadd(5);
-----------------------------------
            when wr12_a =>            -------------------0
				iscl := '0';	-- keep SCL low
--				isda := txd; -- set SDA