init9011.vhd

自己写的iic配置芯片的源程序

--------------------------------------------------------------------------------
--实现了向slave iic machine随机写多个字节，写顺序为
--1.从机地址
--2.偏移地址 1个字节。如果读取两个字节的eeprom，需要两个字节
--3.送出写的数据
--4.等待10ms, 继续循环。

--note:进程里面最好用variable,进程外最好用signal


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity Init9011 is
	port (
		clk : in std_logic;
		ena : in std_logic;
		nReset : in std_logic;
		clk_cnt : in unsigned(7 downto 0);	-- 4x SCL 

		-- input signals
		CFGDONE :out std_logic;
		Dout : out std_logic_vector(7 downto 0);
		ack1,ack2: out std_logic;

		-- i2c signals
		SCL : inout std_logic;
		SDA : inout std_logic;
		--test
		test1:out std_logic;
		test3:out std_logic_vector(4 downto 0)
	);
end entity Init9011;

architecture structural of Init9011 is

    type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, ack1_a, ack1_b, ack1_c, ack1_d,
    ack2_a, ack2_b, ack2_c, ack2_d, ack3_a, ack3_b, ack3_c, ack3_d, ack4_a, ack4_b, ack4_c, ack4_d,
   
    rd1_a, rd1_b, rd1_c, rd1_d, rd2_a, rd2_b, rd2_c, rd2_d, rd3_a, rd3_b, rd3_c, rd3_d, rd4_a, rd4_b, rd4_c, rd4_d, 
    rd5_a, rd5_b, rd5_c, rd5_d, rd6_a, rd6_b, rd6_c, rd6_d, rd7_a, rd7_b, rd7_c, rd7_d, rd8_a, rd8_b, rd8_c, rd8_d, 
    wr1_a, wr1_b, wr1_c, wr1_d, wr2_a, wr2_b, wr2_c, wr2_d, wr3_a, wr3_b, wr3_c, wr3_d, wr4_a, wr4_b, wr4_c, wr4_d,
    wr5_a, wr5_b, wr5_c, wr5_d, wr6_a, wr6_b, wr6_c, wr6_d, wr7_a, wr7_b, wr7_c, wr7_d, wr8_a, wr8_b, wr8_c, wr8_d,  --从机地址
    wr9_a, wr9_b, wr9_c, wr9_d, wr10_a, wr10_b, wr10_c, wr10_d, wr11_a, wr11_b, wr11_c, wr11_d, wr12_a, wr12_b, wr12_c, wr12_d,
    wr13_a, wr13_b, wr13_c, wr13_d, wr14_a, wr14_b, wr14_c, wr14_d, wr15_a, wr15_b, wr15_c, wr15_d, wr16_a, wr16_b, wr16_c, wr16_d, --高字节地址
    wr17_a, wr17_b, wr17_c, wr17_d, wr18_a, wr18_b, wr18_c, wr18_d, wr19_a, wr19_b, wr19_c, wr19_d, wr20_a, wr20_b, wr20_c, wr20_d,
    wr21_a, wr21_b, wr21_c, wr21_d, wr22_a, wr22_b, wr22_c, wr22_d, wr23_a, wr23_b, wr23_c, wr23_d, wr24_a, wr24_b, wr24_c, wr24_d, --写的数据
    wr25_a, wr25_b, wr25_c, wr25_d, wr26_a, wr26_b, wr26_c, wr26_d, wr27_a, wr27_b, wr27_c, wr27_d, wr28_a, wr28_b, wr28_c, wr28_d,
    wr29_a, wr29_b, wr29_c, wr29_d, wr30_a, wr30_b, wr30_c, wr30_d, wr31_a, wr31_b, wr31_c, wr31_d, wr32_a, wr32_b, wr32_c, wr32_d, --低字节地址
    TriState);
	signal state       : cmds;
	signal SDAo, SCLo  : std_logic;
	signal txd         : std_logic;
	signal slave_wait  : std_logic;

	--
	signal WrDone : std_logic ;                  --写完一个字节标志位
	signal cycle  : integer range 0 to 20000;    --等待周期数
	signal i      : integer range 0 to 40;        --标记当前正在写第几个字节

	-- 访问eeprom.address = oxA8.
	signal addwr      : std_logic_vector(7 downto 0); 
	signal subadd     : std_logic_vector(7 downto 0); 
	signal subadd2    : std_logic_vector(7 downto 0);
	signal data       : std_logic_vector(7 downto 0);
	-- 定义数组  每个数组17个字节
	type MatrixAdd     is array(0 to 38) of std_logic_vector(7 downto 0);
	type MatrixSubAdd  is array(0 to 38) of std_logic_vector(7 downto 0);
	type MatrixSubAdd2 is array(0 to 38) of std_logic_vector(7 downto 0);
	type Matrixdata    is array(0 to 38) of std_logic_vector(7 downto 0);
	--定义数组常量
	--9011 address 0x60/68; 9034 address 0x72/7A; eprom address 0xA8
	constant AddSlave : MatrixAdd    :=( X"60",X"60",X"68",X"68",X"68",X"68",X"68",X"60",X"68",X"68",X"68",X"60",X"68",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"60"   ,X"7A",X"72",X"7A",X"72",X"72",X"72",X"72",X"72",X"72",X"72",X"72",X"72",X"72",X"72",X"72",X"72",X"72" );
	constant SubAddr  : MatrixSubAdd :=( X"09",X"05",X"18",X"13",X"14",X"15",X"16",X"08",X"26",X"35",X"38",X"79",X"37",X"88",X"89",X"81",X"B6",X"B7",X"B8",X"B5",X"5F",X"4A"   ,X"3D",X"82",X"2F",X"08",X"79",X"05",X"05",X"48",X"32",X"36",X"37",X"34",X"38",X"39",X"33",X"71",X"75" );
	constant SubAddr2 : MatrixSubAdd2:=( X"68",X"68",X"30",X"31",X"32",X"30",X"31",X"32",X"33",X"34",X"37",X"34",X"37",X"34",X"37",X"34",X"37",X"34",X"37",X"60",X"60",X"09"   ,X"7A",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"72",X"72",X"72",X"72",X"72",X"72",X"72" );
	constant CfgData  : Matrixdata   :=( X"91",X"10",X"54",X"0F",X"20",X"00",X"00",X"07",X"40",X"06",X"0C",X"06",X"03",X"88",X"16",X"C3",X"C1",X"86",X"01",X"02",X"C8",X"0D"   ,X"07",X"25",X"00",X"37",X"01",X"03",X"00",X"00",X"7A",X"D0",X"02",X"24",X"E0",X"01",X"30",X"40",X"40" );
	--                                     0                             5                            10                            15                            20                                25等待输入像素时钟稳定       30                            35                 38  
begin
	-- hookup i2c core
--	u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, core_txd, core_rxd, SCL, SDA);

--for debugger

    test1 <= WrDone;
    test3 <= conv_std_logic_vector(i,5);
	-- 
	process(i)
	begin
	    case (i) is
		  when 1 =>
	         addwr   <= AddSlave(0)(7 downto 0);
             SubAdd  <= SubAddr(0)(7 downto 0);
	         SubAdd2 <= SubAddr2(0)(7 downto 0);
	         Data    <= CfgData(0)(7 downto 0);
		  when 2 =>
	         addwr   <= AddSlave(1)(7 downto 0);
             SubAdd  <= SubAddr(1)(7 downto 0);
	         SubAdd2 <= SubAddr2(1)(7 downto 0);
	         Data    <= CfgData(1)(7 downto 0);
		  when 3 =>
	         addwr   <= AddSlave(2)(7 downto 0);
             SubAdd  <= SubAddr(2)(7 downto 0);
	         SubAdd2 <= SubAddr2(2)(7 downto 0);
	         Data    <= CfgData(2)(7 downto 0);
		  when 4 =>
	         addwr   <= AddSlave(3)(7 downto 0);
             SubAdd  <= SubAddr(3)( 7 downto 0);
	         SubAdd2 <= SubAddr2(3)( 7 downto 0);
	         Data    <= CfgData(3)(7 downto 0);
	      when 5 =>
	         addwr   <= AddSlave(4)(7 downto 0);
             SubAdd  <= SubAddr(4)(7 downto 0);
	         SubAdd2 <= SubAddr2(4)(7 downto 0);
	         Data    <= CfgData(4)(7 downto 0);
		  when 6 =>
	         addwr   <= AddSlave(5)(7 downto 0);
             SubAdd  <= SubAddr(5)(7 downto 0);
	         SubAdd2 <= SubAddr2(5)(7 downto 0);
	         Data    <= CfgData(5)(7 downto 0);
		  when 7 =>
	         addwr   <= AddSlave(6)(7 downto 0);
             SubAdd  <= SubAddr(6)(7 downto 0);
	         SubAdd2 <= SubAddr2(6)(7 downto 0);
	         Data    <= CfgData(6)(7 downto 0);
		  when 8 =>
	         addwr   <= AddSlave(7)(7 downto 0);
             SubAdd  <= SubAddr(7)(7 downto 0);
	         SubAdd2 <= SubAddr2(7)(7 downto 0);
	         Data    <= CfgData(7)(7 downto 0);
		  when 9 =>
	         addwr   <= AddSlave(8)(7 downto 0);
             SubAdd  <= SubAddr(8)(7 downto 0);
	         SubAdd2 <= SubAddr2(8)(7 downto 0);
	         Data    <= CfgData(8)(7 downto 0);
		  when 10 =>
	         addwr   <= AddSlave(9)(7 downto 0);
             SubAdd  <= SubAddr(9)(7 downto 0);
	         SubAdd2 <= SubAddr2(9)(7 downto 0);
	         Data    <= CfgData(9)(7 downto 0);
		  when 11 =>
	         addwr   <= AddSlave(10)(7 downto 0);
             SubAdd  <= SubAddr(10)(7 downto 0);
	         SubAdd2 <= SubAddr2(10)(7 downto 0);
	         Data    <= CfgData(10)(7 downto 0);
	      when 12 =>
	         addwr   <= AddSlave(11)(7 downto 0);
             SubAdd  <= SubAddr(11)(7 downto 0);
	         SubAdd2 <= SubAddr2(11)(7 downto 0);
	         Data    <= CfgData(11)(7 downto 0);
		  when 13 =>
	         addwr   <= AddSlave(12)(7 downto 0);
             SubAdd  <= SubAddr(12)( 7 downto 0);
	         SubAdd2 <= SubAddr2(12)( 7 downto 0);
	         Data    <= CfgData(12)(7 downto 0);
	      when 14 =>
	         addwr   <= AddSlave(13)(7 downto 0);
             SubAdd  <= SubAddr(13)(7 downto 0);
	         SubAdd2 <= SubAddr2(13)(7 downto 0);
	         Data    <= CfgData(13)(7 downto 0);
		  when 15 =>
	         addwr   <= AddSlave(14)(7 downto 0);
             SubAdd  <= SubAddr(14)(7 downto 0);
	         SubAdd2 <= SubAddr2(14)(7 downto 0);
	         Data    <= CfgData(14)(7 downto 0);
		  when 16 =>
	         addwr   <= AddSlave(15)(7 downto 0);
             SubAdd  <= SubAddr(15)(7 downto 0);
	         SubAdd2 <= SubAddr2(15)(7 downto 0);
	         Data    <= CfgData(15)(7 downto 0);
		  when 17 =>
	         addwr   <= AddSlave(16)(7 downto 0);
             SubAdd  <= SubAddr(16)(7 downto 0);
	         SubAdd2 <= SubAddr2(16)(7 downto 0);
	         Data    <= CfgData(16)(7 downto 0);
		  when 18 =>
	         addwr   <= AddSlave(17)(7 downto 0);
             SubAdd  <= SubAddr(17)(7 downto 0);
	         SubAdd2 <= SubAddr2(17)(7 downto 0);
	         Data    <= CfgData(17)(7 downto 0);
		  when 19 =>
	         addwr   <= AddSlave(18)(7 downto 0);
             SubAdd  <= SubAddr(18)(7 downto 0);
	         SubAdd2 <= SubAddr2(18)(7 downto 0);
	         Data    <= CfgData(18)(7 downto 0);
		  when 20 =>
	         addwr   <= AddSlave(19)(7 downto 0);
             SubAdd  <= SubAddr(19)( 7 downto 0);
	         SubAdd2 <= SubAddr2(19)( 7 downto 0);
	         Data    <= CfgData(19)(7 downto 0);
		  when 21 =>
	         addwr   <= AddSlave(20)(7 downto 0);
             SubAdd  <= SubAddr(20)( 7 downto 0);
	         SubAdd2 <= SubAddr2(20)( 7 downto 0);
	         Data    <= CfgData(20)(7 downto 0);
		  when 22 =>
	         addwr   <= AddSlave(21)(7 downto 0);
             SubAdd  <= SubAddr(21)( 7 downto 0);
	         SubAdd2 <= SubAddr2(21)( 7 downto 0);
	         Data    <= CfgData(21)(7 downto 0);
		  when 23 =>
	         addwr   <= AddSlave(22)(7 downto 0);
             SubAdd  <= SubAddr(22)( 7 downto 0);
	         SubAdd2 <= SubAddr2(22)( 7 downto 0);
	         Data    <= CfgData(22)(7 downto 0);
		  when 24 =>
	         addwr   <= AddSlave(23)(7 downto 0);
             SubAdd  <= SubAddr(23)( 7 downto 0);
	         SubAdd2 <= SubAddr2(23)( 7 downto 0);
	         Data    <= CfgData(23)(7 downto 0);
		  when 25 =>
	         addwr   <= AddSlave(24)(7 downto 0);
             SubAdd  <= SubAddr(24)( 7 downto 0);
	         SubAdd2 <= SubAddr2(24)( 7 downto 0);
	         Data    <= CfgData(24)(7 downto 0);
		  when 26 =>
	         addwr   <= AddSlave(25)(7 downto 0);
             SubAdd  <= SubAddr(25)(7 downto 0);
	         SubAdd2 <= SubAddr2(25)(7 downto 0);
	         Data    <= CfgData(25)(7 downto 0);
		  when 27 =>
	         addwr   <= AddSlave(26)(7 downto 0);
             SubAdd  <= SubAddr(26)(7 downto 0);
	         SubAdd2 <= SubAddr2(26)(7 downto 0);
	         Data    <= CfgData(26)(7 downto 0);
		  when 28 =>
	         addwr   <= AddSlave(27)(7 downto 0);
             SubAdd  <= SubAddr(27)(7 downto 0);
	         SubAdd2 <= SubAddr2(27)(7 downto 0);
	         Data    <= CfgData(27)(7 downto 0);
		  when 29 =>
	         addwr   <= AddSlave(28)(7 downto 0);
             SubAdd  <= SubAddr(28)( 7 downto 0);
	         SubAdd2 <= SubAddr2(28)( 7 downto 0);
	         Data    <= CfgData(28)(7 downto 0);
		  when 30 =>
	         addwr   <= AddSlave(29)(7 downto 0);
             SubAdd  <= SubAddr(29)( 7 downto 0);
	         SubAdd2 <= SubAddr2(29)( 7 downto 0);
	         Data    <= CfgData(29)(7 downto 0);
		  when 31 =>
	         addwr   <= AddSlave(30)(7 downto 0);
             SubAdd  <= SubAddr(30)( 7 downto 0);
	         SubAdd2 <= SubAddr2(30)( 7 downto 0);
	         Data    <= CfgData(30)(7 downto 0);
		  when 32 =>
	         addwr   <= AddSlave(31)(7 downto 0);
             SubAdd  <= SubAddr(31)( 7 downto 0);
	         SubAdd2 <= SubAddr2(31)( 7 downto 0);
	         Data    <= CfgData(31)(7 downto 0);
		  when 33 =>
	         addwr   <= AddSlave(32)(7 downto 0);
             SubAdd  <= SubAddr(32)( 7 downto 0);
	         SubAdd2 <= SubAddr2(32)( 7 downto 0);
	         Data    <= CfgData(32)(7 downto 0);
		  when 34 =>
	         addwr   <= AddSlave(33)(7 downto 0);
             SubAdd  <= SubAddr(33)( 7 downto 0);
	         SubAdd2 <= SubAddr2(33)( 7 downto 0);
	         Data    <= CfgData(33)(7 downto 0);
		  when 35 =>
	         addwr   <= AddSlave(34)(7 downto 0);
             SubAdd  <= SubAddr(34)( 7 downto 0);
	         SubAdd2 <= SubAddr2(34)( 7 downto 0);
	         Data    <= CfgData(34)(7 downto 0);
		  when 36 =>
	         addwr   <= AddSlave(35)(7 downto 0);
             SubAdd  <= SubAddr(35)( 7 downto 0);
	         SubAdd2 <= SubAddr2(35)( 7 downto 0);
	         Data    <= CfgData(35)(7 downto 0);
		  when 37 =>
	         addwr   <= AddSlave(36)(7 downto 0);
             SubAdd  <= SubAddr(36)( 7 downto 0);
	         SubAdd2 <= SubAddr2(36)( 7 downto 0);
	         Data    <= CfgData(36)(7 downto 0);
		  when 38 =>
	         addwr   <= AddSlave(37)(7 downto 0);
             SubAdd  <= SubAddr(37)( 7 downto 0);
	         SubAdd2 <= SubAddr2(37)( 7 downto 0);
	         Data    <= CfgData(37)(7 downto 0);
		  when 39 =>
	         addwr   <= AddSlave(38)(7 downto 0);
             SubAdd  <= SubAddr(38)( 7 downto 0);
	         SubAdd2 <= SubAddr2(38)( 7 downto 0);
	         Data    <= CfgData(38)(7 downto 0);

	     when others => null;
	   end case;
	end process;

	--
	-- state machine
	--
   -- generate statemachine
	nxt_state_decoder : process (clk, nReset, state,  SDA)
		variable nxt_state : cmds;
		variable icmd_ack, ibusy, store_sda : std_logic;
		variable itxd : std_logic;
		--
		variable done    : std_logic := '0';            --写完一个字节标志位
	    variable vcycle  : integer range 0 to 20000;    --等待周期数
	    variable vi      : integer range 0 to 30:=0;    --标记当前正在写第几个字节
	begin

		case (state) is
			-- idle
			-- start
			when idle =>
				nxt_state := start_a;
			    done := '0';
			when start_a =>
				nxt_state := start_b;

			when start_b =>
				nxt_state := start_c;

			when start_c =>
				nxt_state := start_d;

			when start_d =>
				nxt_state := wr1_a;
				ibusy := '0'; -- not busy when idle
	-------------------------------------------------写从机地址----------------			
		    when wr1_a =>  --first bit
				nxt_state := wr1_b;

			when wr1_b =>
				nxt_state := wr1_c;

			when wr1_c =>
				nxt_state := wr1_d;

			when wr1_d =>
				nxt_state := wr2_a;
			--	ibusy := '0'; -- not busy when idle
-------------------------------			
			 when wr2_a =>
				nxt_state := wr2_b;

			when wr2_b =>
				nxt_state := wr2_c;

			when wr2_c =>
				nxt_state := wr2_d;

			when wr2_d =>
				nxt_state := wr3_a;
--------------------------			
			
			when wr3_a =>
				nxt_state := wr3_b;

			when wr3_b =>
				nxt_state := wr3_c;

			when wr3_c =>
				nxt_state := wr3_d;

			when wr3_d =>
				nxt_state := wr4_a;
			--	ibusy := '0'; -- not busy when idle
	-----------------------		
			
			when wr4_a =>
				nxt_state := wr4_b;

			when wr4_b =>
				nxt_state := wr4_c;

			when wr4_c =>
				nxt_state := wr4_d;

			when wr4_d =>
				nxt_state := wr5_a;
-----------------------				
		    when wr5_a =>
				nxt_state := wr5_b;

			when wr5_b =>
				nxt_state := wr5_c;

			when wr5_c =>
				nxt_state := wr5_d;

			when wr5_d =>
				nxt_state := wr6_a;
------------------------
             when wr6_a =>
				nxt_state := wr6_b;

			when wr6_b =>
				nxt_state := wr6_c;

			when wr6_c =>
				nxt_state := wr6_d;

			when wr6_d =>
				nxt_state := wr7_a;	
	----------------------------			
				
		     when wr7_a =>
				nxt_state := wr7_b;

			when wr7_b =>
				nxt_state := wr7_c;

			when wr7_c =>
				nxt_state := wr7_d;

			when wr7_d =>
				nxt_state := wr8_a;		
				
				
		    when wr8_a =>
				nxt_state := wr8_b;

			when wr8_b =>
				nxt_state := wr8_c;

			when wr8_c =>
				nxt_state := wr8_d;

			when wr8_d =>
				nxt_state := ack1_a;
------------------------------				
			when ack1_a =>
				nxt_state := ack1_b;

			when ack1_b=>
				nxt_state := ack1_c;

			when ack1_c =>
				nxt_state := ack1_d;

			when ack1_d =>
				nxt_state := wr9_a;		
---------------------------------------写入高位字节地址---------------------			
			when wr9_a =>
				nxt_state := wr9_b;

			when wr9_b =>
				nxt_state := wr9_c;

			when wr9_c =>
				nxt_state := wr9_d;

			when wr9_d =>
				nxt_state := wr10_a;	
	---------------------------------			
			when wr10_a =>
				nxt_state := wr10_b;

			when wr10_b =>
				nxt_state := wr10_c;

			when wr10_c =>
				nxt_state := wr10_d;

			when wr10_d =>
				nxt_state := wr11_a;
	--------------------------	
	       when wr11_a =>
				nxt_state := wr11_b;

			when wr11_b =>
				nxt_state := wr11_c;

			when wr11_c =>
				nxt_state := wr11_d;

			when wr11_d =>
				nxt_state := wr12_a;
   --------------------------
           when wr12_a =>
				nxt_state := wr12_b;

			when wr12_b =>
				nxt_state := wr12_c;

			when wr12_c =>
				nxt_state := wr12_d;

			when wr12_d =>
				nxt_state := wr13_a;
				-------------
			when wr13_a =>
				nxt_state := wr13_b;

			when wr13_b =>
				nxt_state := wr13_c;

			when wr13_c =>
				nxt_state := wr13_d;

			when wr13_d =>
				nxt_state := wr14_a;
				---------
			when wr14_a =>
				nxt_state := wr14_b;

			when wr14_b =>
				nxt_state := wr14_c;

			when wr14_c =>
				nxt_state := wr14_d;

			when wr14_d =>
				nxt_state := wr15_a;	
				------------
			when wr15_a =>
				nxt_state := wr15_b;

			when wr15_b =>
				nxt_state := wr15_c;

			when wr15_c =>
				nxt_state := wr15_d;

			when wr15_d =>
				nxt_state := wr16_a;
				-----------
		    when wr16_a =>
				nxt_state := wr16_b;

			when wr16_b =>
				nxt_state := wr16_c;

			when wr16_c =>
				nxt_state := wr16_d;

			when wr16_d =>
				nxt_state := ack2_a;	
				-------------------------				
		    when ack2_a =>
				nxt_state := ack2_b;

			when ack2_b=>
				nxt_state := ack2_c;

			when ack2_c =>
				nxt_state := ack2_d;

			when ack2_d =>
				nxt_state := wr17_a;   	--写eeprom时进入wr25_a，写9011/ 9034时进入wr17_a
--------------------------------------写低位字节地址--------------------------------------------------