v_fpga.tan.rpt

自己写的iic配置芯片的源程序

; Total number of failed paths ;           ;                                  ;                                  ;                               ;                       ;            ;          ; 1            ;
+------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------+-----------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F672C7       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 27 MHz             ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK27           ;                    ; User Pin ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK27'                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------+----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                               ; To                                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------+----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 1.304 ns                                ; 29.04 MHz ( period = 34.430 ns )                    ; Init9011:inst1|data[3]                                                                             ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.301 ns                  ; 2.997 ns                ;
; 1.465 ns                                ; 29.32 MHz ( period = 34.108 ns )                    ; Init9011:inst1|subadd[5]                                                                           ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.297 ns                  ; 2.832 ns                ;
; 1.477 ns                                ; 29.34 MHz ( period = 34.084 ns )                    ; Init9011:inst1|subadd[3]                                                                           ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.247 ns                  ; 2.770 ns                ;
; 1.570 ns                                ; 29.50 MHz ( period = 33.898 ns )                    ; Init9011:inst1|addwr[1]                                                                            ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.250 ns                  ; 2.680 ns                ;
; 1.622 ns                                ; 29.59 MHz ( period = 33.794 ns )                    ; Init9011:inst1|data[6]                                                                             ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.247 ns                  ; 2.625 ns                ;
; 1.646 ns                                ; 29.63 MHz ( period = 33.746 ns )                    ; Init9011:inst1|subadd[0]                                                                           ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.292 ns                  ; 2.646 ns                ;
; 1.658 ns                                ; 29.65 MHz ( period = 33.722 ns )                    ; Init9011:inst1|addwr[3]                                                                            ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.311 ns                  ; 2.653 ns                ;
; 1.659 ns                                ; 29.66 MHz ( period = 33.720 ns )                    ; Init9011:inst1|data[0]                                                                             ; Init9011:inst1|SDAo                    ; CLK27      ; CLK27    ; 18.519 ns                   ; 4.297 ns                  ; 2.638 ns                ;