v_fpga.fit.eqn

自己写的iic配置芯片的源程序

HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[1] = HB1_q_a[10]_PORT_A_data_out[13];

--HB1_q_a[9] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[9] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[9] = HB1_q_a[10]_PORT_A_data_out[12];

--HB1_q_a[2] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[2] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[2] = HB1_q_a[10]_PORT_A_data_out[11];

--HB1_q_a[5] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[5] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[5] = HB1_q_a[10]_PORT_A_data_out[10];

--HB1_q_a[6] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[6] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[6] = HB1_q_a[10]_PORT_A_data_out[9];

--HB1_q_a[16] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[16] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[16] = HB1_q_a[10]_PORT_A_data_out[8];

--HB1_q_a[17] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[17] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[17] = HB1_q_a[10]_PORT_A_data_out[7];

--HB1_q_a[15] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[15] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[15] = HB1_q_a[10]_PORT_A_data_out[6];

--HB1_q_a[14] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[14] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[14] = HB1_q_a[10]_PORT_A_data_out[5];

--HB1_q_a[13] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[13] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[13] = HB1_q_a[10]_PORT_A_data_out[4];

--HB1_q_a[12] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[12] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[12] = HB1_q_a[10]_PORT_A_data_out[3];

--HB1_q_a[11] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[11] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[11] = HB1_q_a[10]_PORT_A_data_out[2];

--HB1_q_a[0] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[0] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[0] = HB1_q_a[10]_PORT_A_data_out[1];


--JB6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X8_Y19_N2
--operation mode is normal

JB6_Q[0] = AMPP_FUNCTION(!A1L7, altera_internal_jtag, G1_CLRN_SIGNAL, G1L16);


--LB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X6_Y19_N1
--operation mode is normal

LB1_state[4] = AMPP_FUNCTION(!A1L7, LB1_state[3], LB1_state[4], LB1_state[7], VCC, !A1L9);


--LB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LC_X6_Y19_N4
--operation mode is normal

LB1_state[3] = AMPP_FUNCTION(!A1L7, A1L9, LB1_state[2], VCC);


--G1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X8_Y20_N8
--operation mode is normal

G1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L7, A1L109, P5_dffs[0], P5_dffs[1], A1L108, LB1_state[0], LB1_state[12]);


--LB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] at LC_X9_Y19_N4
--operation mode is normal

LB1_state[8] = AMPP_FUNCTION(!A1L7, LB1_state[7], LB1_state[5], VCC, A1L9);


--B1_bypass_reg_out is sld_signaltap:auto_signaltap_0|bypass_reg_out at LC_X6_Y21_N0
--operation mode is normal

B1_bypass_reg_out = AMPP_FUNCTION(!A1L7, B1_bypass_reg_out, G1L27, altera_internal_jtag, !B1_reset_all);


--JB4_Q[5] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] at LC_X6_Y21_N4
--operation mode is normal

JB4_Q[5] = AMPP_FUNCTION(!A1L7, JB2_Q[0], JB3_Q[5], JB5_Q[5], G1_CLRN_SIGNAL, G1L19);


--JB4_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] at LC_X6_Y21_N9
--operation mode is normal

JB4_Q[3] = AMPP_FUNCTION(!A1L7, JB2_Q[0], JB5_Q[3], JB3_Q[3], G1_CLRN_SIGNAL, G1L19);


--JB4_Q[4] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] at LC_X6_Y21_N7
--operation mode is normal

JB4_Q[4] = AMPP_FUNCTION(!A1L7, JB2_Q[0], JB3_Q[4], JB5_Q[4], G1_CLRN_SIGNAL, G1L19);


--G1L12 is sld_hub:sld_hub_inst|hub_tdo~457 at LC_X6_Y21_N5
--operation mode is normal

G1L12 = AMPP_FUNCTION(JB4_Q[5], JB4_Q[3], JB4_Q[4], B1_bypass_reg_out);


--K1_WORD_SR[0] is sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] at LC_X8_Y22_N0
--operation mode is normal

K1_WORD_SR[0] = AMPP_FUNCTION(!A1L7, LB1_state[4], K2_clear_signal, K1L15, K1_WORD_SR[1], VCC, K1L13);


--G1L13 is sld_hub:sld_hub_inst|hub_tdo~458 at LC_X6_Y22_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1L13 = AMPP_FUNCTION(JB4_Q[3], JB4_Q[5], K1_WORD_SR[0]);

--P1_dffs[0] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[0] at LC_X6_Y22_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

P1_dffs[0] = AMPP_FUNCTION(!A1L7, P1_dffs[1], !B1_reset_all, GND, L1_trigger_setup_ena);


--P4_dffs[0] is sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] at LC_X13_Y19_N9
--operation mode is normal

P4_dffs[0] = AMPP_FUNCTION(!A1L7, M1_is_max_write_address_ff, P4_dffs[1], B1L28, !B1_reset_all);


--LB1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 at LC_X7_Y19_N9
--operation mode is normal

LB1L18 = AMPP_FUNCTION(LB1_state[3], LB1_state[4]);


--G1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG at LC_X8_Y19_N6
--operation mode is normal

G1_HUB_BYPASS_REG = AMPP_FUNCTION(!A1L7, LB1_state[4], altera_internal_jtag, VCC);


--MB1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_bje:auto_generated|dffe1a[0] at LC_X7_Y21_N3
--operation mode is normal

MB1_dffe1a[0] = AMPP_FUNCTION(!A1L7, JB3_Q[1], G1L25, JB3_Q[2], JB3_Q[3], G1_CLRN_SIGNAL, G1L3);


--K2L19Q is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]~748 at LC_X7_Y22_N3
--operation mode is normal

K2L19Q = AMPP_FUNCTION(!A1L7, K2L21Q, K2_clear_signal, LB1_state[4], K2L23Q, VCC, K2L22);


--K2L20Q is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]~749 at LC_X7_Y22_N6
--operation mode is normal

K2L20Q = AMPP_FUNCTION(!A1L7, K2_word_counter[4], K2L26, K1L16, K2L27, VCC, K2L22);


--G1L14 is sld_hub:sld_hub_inst|hub_tdo~460 at LC_X7_Y22_N7
--operation mode is normal

G1L14 = AMPP_FUNCTION(K2L19Q, K2L20Q, G1_HUB_BYPASS_REG, MB1_dffe1a[0]);


--JB3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] at LC_X7_Y20_N4
--operation mode is normal

JB3_Q[0] = AMPP_FUNCTION(!A1L7, LB1_state[4], L1L3, JB3_Q[1], G1_CLRN_SIGNAL, JB3L4);


--E1_SCLo is sim_i2c:inst3|SCLo at LC_X8_Y16_N4
--operation mode is normal

E1_SCLo_lut_out = !E1L129 & !E1L146 & !E1L139 & !E1L134;
E1_SCLo = DFFEAS(E1_SCLo_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_SDAo is sim_i2c:inst3|SDAo at LC_X6_Y16_N2
--operation mode is normal

E1_SDAo_lut_out = !E1L171 & !E1L151 & !E1L156 & !E1L163;
E1_SDAo = DFFEAS(E1_SDAo_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1L119Q is sim_i2c:inst3|output_decoder~1 at LC_X1_Y16_N3
--operation mode is normal

E1L119Q_lut_out = E1L123 # E1_state.ack2_d # E1_state.ack1_d # !E1L122;
E1L119Q = DFFEAS(E1L119Q_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_cycle[13] is sim_i2c:inst3|cycle[13] at LC_X9_Y11_N8
--operation mode is normal

E1_cycle[13]_lut_out = E1L31;
E1_cycle[13] = DFFEAS(E1_cycle[13]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, , , , );


--E1_cycle[12] is sim_i2c:inst3|cycle[12] at LC_X8_Y10_N2
--operation mode is normal

E1_cycle[12]_lut_out = E1L34;
E1_cycle[12] = DFFEAS(E1_cycle[12]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, , , , );


--E1_cycle[11] is sim_i2c:inst3|cycle[11] at LC_X8_Y11_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cycle[11]_lut_out = GND;
E1_cycle[11] = DFFEAS(E1_cycle[11]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, E1L37, , , VCC);


--E1_cycle[9] is sim_i2c:inst3|cycle[9] at LC_X9_Y10_N3
--operation mode is normal

E1_cycle[9]_lut_out = E1L42;
E1_cycle[9] = DFFEAS(E1_cycle[9]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, , , , );


--E1_cycle[8] is sim_i2c:inst3|cycle[8] at LC_X9_Y10_N9
--operation mode is normal

E1_cycle[8]_lut_out = E1L45;
E1_cycle[8] = DFFEAS(E1_cycle[8]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, , , , );


--E1_cycle[7] is sim_i2c:inst3|cycle[7] at LC_X9_Y10_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cycle[7]_lut_out = GND;
E1_cycle[7] = DFFEAS(E1_cycle[7]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, E1L48, , , VCC);


--E1_cycle[5] is sim_i2c:inst3|cycle[5] at LC_X12_Y12_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cycle[5]_lut_out = GND;
E1_cycle[5] = DFFEAS(E1_cycle[5]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, E1L53, , , VCC);


--E1_cycle[4] is sim_i2c:inst3|cycle[4] at LC_X12_Y12_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cycle[4]_lut_out = GND;
E1_cycle[4] = DFFEAS(E1_cycle[4]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, E1L56, , , VCC);


--E1_cycle[3] is sim_i2c:inst3|cycle[3] at LC_X9_Y12_N1
--operation mode is normal

E1_cycle[3]_lut_out = E1L59 & (!A1L111 # !A1L110 # !A1L113);
E1_cycle[3] = DFFEAS(E1_cycle[3]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, , , , );


--E1_cycle[0] is sim_i2c:inst3|cycle[0] at LC_X9_Y12_N0
--operation mode is normal

E1_cycle[0]_lut_out = E1L65 & (!A1L111 # !A1L110 # !A1L113);
E1_cycle[0] = DFFEAS(E1_cycle[0]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, , , , );


--E1_cycle[1] is sim_i2c:inst3|cycle[1] at LC_X9_Y10_N7
--operation mode is normal

E1_cycle[1]_lut_out = E1L68 & (!A1L111 # !A1L113 # !A1L110);
E1_cycle[1] = DFFEAS(E1_cycle[1]_lut_out, GLOBAL(F1_en), VCC, , E1_WrDone, , , , );


--G1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL at LC_X6_Y19_N7
--operation mode is normal

G1_CLRN_SIGNAL = AMPP_FUNCTION(!A1L7, LB1_state[1], JB1_Q[0], VCC);


--G1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q at LC_X6_Y19_N0
--operation mode is normal

G1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(!A1L7, G1_OK_TO_UPDATE_IR_Q, LB1_state[8], LB1_state[4], G1_jtag_debug_mode_usr1, VCC);


--G1L16 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~29 at LC_X6_Y19_N5
--operation mode is normal

G1L16 = AMPP_FUNCTION(G1_jtag_debug_mode_usr1, LB1_state[4], A1L9, G1_OK_TO_UPDATE_IR_Q);


--LB1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7] at LC_X9_Y20_N5
--operation mode is normal

LB1_state[7] = AMPP_FUNCTION(!A1L7, LB1_state[6], A1L9, VCC);


--LB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] at LC_X9_Y19_N5
--operation mode is normal

LB1_state[2] = AMPP_FUNCTION(!A1L7, LB1_state[8], LB1_state[1], LB1_state[15], VCC, A1L9);


--P5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] at LC_X9_Y20_N4
--operation mode is normal

P5_dffs[1] = AMPP_FUNCTION(!A1L7, P5_dffs[2], LB1_state[0], LB1_state[11]);


--P5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] at LC_X8_Y20_N7
--operation mode is normal

P5_dffs[9] = AMPP_FUNCTION(!A1L7, altera_internal_jtag, LB1_state[0], LB1_state[11]);


--P5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] at LC_X8_Y20_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

P5_dffs[7] = AMPP_FUNCTION(!A1L7, P5_dffs[8], LB1_state[0], GND, LB1_state[11]);