v_fpga.fit.eqn

自己写的iic配置芯片的源程序

F1L78 = CARRY(!F1L84 # !F1_b[7]);


--F1L79 is counter:inst6|add~627 at LC_X18_Y21_N5
--operation mode is arithmetic

F1L79_carry_eqn = F1L95;
F1L79 = F1_b[3] $ F1L79_carry_eqn;

--F1L80 is counter:inst6|add~629 at LC_X18_Y21_N5
--operation mode is arithmetic

F1L80_cout_0 = !F1L95 # !F1_b[3];
F1L80 = CARRY(F1L80_cout_0);

--F1L81 is counter:inst6|add~629COUT1_668 at LC_X18_Y21_N5
--operation mode is arithmetic

F1L81_cout_1 = !F1L95 # !F1_b[3];
F1L81 = CARRY(F1L81_cout_1);


--F1L82 is counter:inst6|add~632 at LC_X18_Y21_N8
--operation mode is arithmetic

F1L82_carry_eqn = (!F1L95 & F1L86) # (F1L95 & F1L87);
F1L82 = F1_b[6] $ !F1L82_carry_eqn;

--F1L83 is counter:inst6|add~634 at LC_X18_Y21_N8
--operation mode is arithmetic

F1L83_cout_0 = F1_b[6] & !F1L86;
F1L83 = CARRY(F1L83_cout_0);

--F1L84 is counter:inst6|add~634COUT1_671 at LC_X18_Y21_N8
--operation mode is arithmetic

F1L84_cout_1 = F1_b[6] & !F1L87;
F1L84 = CARRY(F1L84_cout_1);


--F1L85 is counter:inst6|add~637 at LC_X18_Y21_N7
--operation mode is arithmetic

F1L85_carry_eqn = (!F1L95 & F1L89) # (F1L95 & F1L90);
F1L85 = F1_b[5] $ (F1L85_carry_eqn);

--F1L86 is counter:inst6|add~639 at LC_X18_Y21_N7
--operation mode is arithmetic

F1L86_cout_0 = !F1L89 # !F1_b[5];
F1L86 = CARRY(F1L86_cout_0);

--F1L87 is counter:inst6|add~639COUT1_670 at LC_X18_Y21_N7
--operation mode is arithmetic

F1L87_cout_1 = !F1L90 # !F1_b[5];
F1L87 = CARRY(F1L87_cout_1);


--F1L88 is counter:inst6|add~642 at LC_X18_Y21_N6
--operation mode is arithmetic

F1L88_carry_eqn = (!F1L95 & F1L80) # (F1L95 & F1L81);
F1L88 = F1_b[4] $ !F1L88_carry_eqn;

--F1L89 is counter:inst6|add~644 at LC_X18_Y21_N6
--operation mode is arithmetic

F1L89_cout_0 = F1_b[4] & !F1L80;
F1L89 = CARRY(F1L89_cout_0);

--F1L90 is counter:inst6|add~644COUT1_669 at LC_X18_Y21_N6
--operation mode is arithmetic

F1L90_cout_1 = F1_b[4] & !F1L81;
F1L90 = CARRY(F1L90_cout_1);


--F1L91 is counter:inst6|add~647 at LC_X18_Y21_N3
--operation mode is arithmetic

F1L91 = F1_b[1] $ (F1L97);

--F1L92 is counter:inst6|add~649 at LC_X18_Y21_N3
--operation mode is arithmetic

F1L92_cout_0 = !F1L97 # !F1_b[1];
F1L92 = CARRY(F1L92_cout_0);

--F1L93 is counter:inst6|add~649COUT1_667 at LC_X18_Y21_N3
--operation mode is arithmetic

F1L93_cout_1 = !F1L98 # !F1_b[1];
F1L93 = CARRY(F1L93_cout_1);


--F1L94 is counter:inst6|add~652 at LC_X18_Y21_N4
--operation mode is arithmetic

F1L94 = F1_b[2] $ !F1L92;

--F1L95 is counter:inst6|add~654 at LC_X18_Y21_N4
--operation mode is arithmetic

F1L95 = CARRY(F1_b[2] & !F1L93);


--F1L96 is counter:inst6|add~657 at LC_X18_Y21_N2
--operation mode is arithmetic

F1L96 = !F1_b[0];

--F1L97 is counter:inst6|add~659 at LC_X18_Y21_N2
--operation mode is arithmetic

F1L97_cout_0 = F1_b[0];
F1L97 = CARRY(F1L97_cout_0);

--F1L98 is counter:inst6|add~659COUT1_666 at LC_X18_Y21_N2
--operation mode is arithmetic

F1L98_cout_1 = F1_b[0];
F1L98 = CARRY(F1L98_cout_1);


--E1L95 is sim_i2c:inst3|done~8 at LC_X5_Y16_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.stop_a_qfbk = E1_state.stop_a;
E1L95 = !E1_state.stop_a_qfbk & !E1_state.stop_b;

--E1_state.stop_a is sim_i2c:inst3|state.stop_a at LC_X5_Y16_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.stop_a = DFFEAS(E1L95, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_state.ack3_d, , , VCC);


--E1L120 is sim_i2c:inst3|reduce_or~450 at LC_X5_Y16_N6
--operation mode is normal

E1L120 = E1_state.stop_a # E1_state.stop_b # !E1_state.idle;


--E1_\nxt_state_decoder:vi[3] is sim_i2c:inst3|\nxt_state_decoder:vi[3] at LC_X12_Y8_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vi[3]_lut_out = GND;
E1_\nxt_state_decoder:vi[3] = DFFEAS(E1_\nxt_state_decoder:vi[3]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_i[3], , , VCC);


--E1_\nxt_state_decoder:vi[2] is sim_i2c:inst3|\nxt_state_decoder:vi[2] at LC_X9_Y8_N5
--operation mode is normal

E1_\nxt_state_decoder:vi[2]_lut_out = E1_i[2];
E1_\nxt_state_decoder:vi[2] = DFFEAS(E1_\nxt_state_decoder:vi[2]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_\nxt_state_decoder:vi[1] is sim_i2c:inst3|\nxt_state_decoder:vi[1] at LC_X9_Y8_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vi[1]_lut_out = GND;
E1_\nxt_state_decoder:vi[1] = DFFEAS(E1_\nxt_state_decoder:vi[1]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_i[1], , , VCC);


--E1L112 is sim_i2c:inst3|LessThan~65 at LC_X12_Y8_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vi[4]_qfbk = E1_\nxt_state_decoder:vi[4];
E1L112 = E1_\nxt_state_decoder:vi[4]_qfbk & (E1_\nxt_state_decoder:vi[3] # E1_\nxt_state_decoder:vi[2] & E1_\nxt_state_decoder:vi[1]);

--E1_\nxt_state_decoder:vi[4] is sim_i2c:inst3|\nxt_state_decoder:vi[4] at LC_X12_Y8_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vi[4] = DFFEAS(E1L112, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_i[4], , , VCC);


--E1_\nxt_state_decoder:vcycle[13] is sim_i2c:inst3|\nxt_state_decoder:vcycle[13] at LC_X12_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[13]_lut_out = GND;
E1_\nxt_state_decoder:vcycle[13] = DFFEAS(E1_\nxt_state_decoder:vcycle[13]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[13], , , VCC);


--E1_\nxt_state_decoder:vcycle[12] is sim_i2c:inst3|\nxt_state_decoder:vcycle[12] at LC_X8_Y10_N4
--operation mode is normal

E1_\nxt_state_decoder:vcycle[12]_lut_out = E1_cycle[12];
E1_\nxt_state_decoder:vcycle[12] = DFFEAS(E1_\nxt_state_decoder:vcycle[12]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_\nxt_state_decoder:vcycle[11] is sim_i2c:inst3|\nxt_state_decoder:vcycle[11] at LC_X8_Y11_N2
--operation mode is normal

E1_\nxt_state_decoder:vcycle[11]_lut_out = E1_cycle[11];
E1_\nxt_state_decoder:vcycle[11] = DFFEAS(E1_\nxt_state_decoder:vcycle[11]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1L114 is sim_i2c:inst3|nxt_state~123 at LC_X12_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[14]_qfbk = E1_\nxt_state_decoder:vcycle[14];
E1L114 = E1_\nxt_state_decoder:vcycle[11] # E1_\nxt_state_decoder:vcycle[12] # E1_\nxt_state_decoder:vcycle[14]_qfbk # E1_\nxt_state_decoder:vcycle[13];

--E1_\nxt_state_decoder:vcycle[14] is sim_i2c:inst3|\nxt_state_decoder:vcycle[14] at LC_X12_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[14] = DFFEAS(E1L114, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[14], , , VCC);


--E1_\nxt_state_decoder:vcycle[9] is sim_i2c:inst3|\nxt_state_decoder:vcycle[9] at LC_X12_Y8_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[9]_lut_out = GND;
E1_\nxt_state_decoder:vcycle[9] = DFFEAS(E1_\nxt_state_decoder:vcycle[9]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[9], , , VCC);


--E1_\nxt_state_decoder:vcycle[8] is sim_i2c:inst3|\nxt_state_decoder:vcycle[8] at LC_X9_Y10_N4
--operation mode is normal

E1_\nxt_state_decoder:vcycle[8]_lut_out = E1_cycle[8];
E1_\nxt_state_decoder:vcycle[8] = DFFEAS(E1_\nxt_state_decoder:vcycle[8]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_\nxt_state_decoder:vcycle[7] is sim_i2c:inst3|\nxt_state_decoder:vcycle[7] at LC_X9_Y10_N8
--operation mode is normal

E1_\nxt_state_decoder:vcycle[7]_lut_out = E1_cycle[7];
E1_\nxt_state_decoder:vcycle[7] = DFFEAS(E1_\nxt_state_decoder:vcycle[7]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1L115 is sim_i2c:inst3|nxt_state~124 at LC_X12_Y8_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[10]_qfbk = E1_\nxt_state_decoder:vcycle[10];
E1L115 = E1_\nxt_state_decoder:vcycle[7] # E1_\nxt_state_decoder:vcycle[8] # E1_\nxt_state_decoder:vcycle[10]_qfbk # E1_\nxt_state_decoder:vcycle[9];

--E1_\nxt_state_decoder:vcycle[10] is sim_i2c:inst3|\nxt_state_decoder:vcycle[10] at LC_X12_Y8_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[10] = DFFEAS(E1L115, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[10], , , VCC);


--E1_\nxt_state_decoder:vcycle[5] is sim_i2c:inst3|\nxt_state_decoder:vcycle[5] at LC_X12_Y12_N6
--operation mode is normal

E1_\nxt_state_decoder:vcycle[5]_lut_out = E1_cycle[5];
E1_\nxt_state_decoder:vcycle[5] = DFFEAS(E1_\nxt_state_decoder:vcycle[5]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_\nxt_state_decoder:vcycle[4] is sim_i2c:inst3|\nxt_state_decoder:vcycle[4] at LC_X12_Y12_N5
--operation mode is normal

E1_\nxt_state_decoder:vcycle[4]_lut_out = E1_cycle[4];
E1_\nxt_state_decoder:vcycle[4] = DFFEAS(E1_\nxt_state_decoder:vcycle[4]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_\nxt_state_decoder:vcycle[3] is sim_i2c:inst3|\nxt_state_decoder:vcycle[3] at LC_X12_Y12_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[3]_lut_out = GND;
E1_\nxt_state_decoder:vcycle[3] = DFFEAS(E1_\nxt_state_decoder:vcycle[3]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[3], , , VCC);


--E1L116 is sim_i2c:inst3|nxt_state~125 at LC_X12_Y8_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[6]_qfbk = E1_\nxt_state_decoder:vcycle[6];
E1L116 = E1_\nxt_state_decoder:vcycle[4] # E1_\nxt_state_decoder:vcycle[5] # E1_\nxt_state_decoder:vcycle[6]_qfbk # !E1_\nxt_state_decoder:vcycle[3];

--E1_\nxt_state_decoder:vcycle[6] is sim_i2c:inst3|\nxt_state_decoder:vcycle[6] at LC_X12_Y8_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[6] = DFFEAS(E1L116, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[6], , , VCC);


--E1L117 is sim_i2c:inst3|nxt_state~126 at LC_X12_Y8_N6
--operation mode is normal

E1L117 = E1L112 # E1L115 # E1L114 # E1L116;


--E1_\nxt_state_decoder:vcycle[0] is sim_i2c:inst3|\nxt_state_decoder:vcycle[0] at LC_X9_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[0]_lut_out = GND;
E1_\nxt_state_decoder:vcycle[0] = DFFEAS(E1_\nxt_state_decoder:vcycle[0]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[0], , , VCC);


--E1_\nxt_state_decoder:vcycle[1] is sim_i2c:inst3|\nxt_state_decoder:vcycle[1] at LC_X9_Y10_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[1]_lut_out = GND;
E1_\nxt_state_decoder:vcycle[1] = DFFEAS(E1_\nxt_state_decoder:vcycle[1]_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[1], , , VCC);


--E1L118 is sim_i2c:inst3|nxt_state~127 at LC_X12_Y8_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[2]_qfbk = E1_\nxt_state_decoder:vcycle[2];
E1L118 = E1L117 # E1_\nxt_state_decoder:vcycle[2]_qfbk # E1_\nxt_state_decoder:vcycle[0] # !E1_\nxt_state_decoder:vcycle[1];

--E1_\nxt_state_decoder:vcycle[2] is sim_i2c:inst3|\nxt_state_decoder:vcycle[2] at LC_X12_Y8_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_\nxt_state_decoder:vcycle[2] = DFFEAS(E1L118, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , E1_cycle[2], , , VCC);


--HB1_q_a[10] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[10] at M512_X26_Y3
--RAM Block Operation Mode: ROM
--Port A Depth: 32, Port A Width: 18
--Port A Logical Depth: 32, Port A Logical Width: 18
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[10] = HB1_q_a[10]_PORT_A_data_out[0];

--HB1_q_a[7] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[7] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[7] = HB1_q_a[10]_PORT_A_data_out[17];

--HB1_q_a[3] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[3] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[3] = HB1_q_a[10]_PORT_A_data_out[16];

--HB1_q_a[4] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[4] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[4] = HB1_q_a[10]_PORT_A_data_out[15];

--HB1_q_a[8] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[8] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );
HB1_q_a[10]_clock_0 = GLOBAL(E1_WrDone);
HB1_q_a[10]_PORT_A_data_out = MEMORY(, , HB1_q_a[10]_PORT_A_address_reg, , , , , , HB1_q_a[10]_clock_0, , , , , );
HB1_q_a[8] = HB1_q_a[10]_PORT_A_data_out[14];

--HB1_q_a[1] is sim_i2c:inst3|altsyncram:Mux_rtl_0|altsyncram_r7l:auto_generated|q_a[1] at M512_X26_Y3
HB1_q_a[10]_PORT_A_address = BUS(E1L107, E1L29, E1L28, E1L27, E1L26);
HB1_q_a[10]_PORT_A_address_reg = DFFE(HB1_q_a[10]_PORT_A_address, HB1_q_a[10]_clock_0, , , );