v_fpga.fit.eqn

自己写的iic配置芯片的源程序

F1_b[19]_lut_out = F1L43;
F1_b[19] = DFFEAS(F1_b[19]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--A1L101 is rtl~459 at LC_X17_Y19_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[22]_qfbk = F1_b[22];
A1L101 = !F1_b[21] & !F1_b[20] & !F1_b[22]_qfbk & !F1_b[19];

--F1_b[22] is counter:inst6|b[22] at LC_X17_Y19_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[22] = DFFEAS(A1L101, GLOBAL(CLK27), VCC, , , F1L35, , , VCC);


--F1_b[17] is counter:inst6|b[17] at LC_X17_Y23_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[17]_lut_out = GND;
F1_b[17] = DFFEAS(F1_b[17]_lut_out, GLOBAL(CLK27), VCC, , , F1L49, , , VCC);


--F1_b[16] is counter:inst6|b[16] at LC_X22_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[16]_lut_out = GND;
F1_b[16] = DFFEAS(F1_b[16]_lut_out, GLOBAL(CLK27), VCC, , , F1L51, , , VCC);


--F1_b[15] is counter:inst6|b[15] at LC_X19_Y22_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[15]_lut_out = GND;
F1_b[15] = DFFEAS(F1_b[15]_lut_out, GLOBAL(CLK27), VCC, , , F1L54, , , VCC);


--A1L102 is rtl~460 at LC_X17_Y19_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[18]_qfbk = F1_b[18];
A1L102 = !F1_b[17] & !F1_b[15] & !F1_b[18]_qfbk & !F1_b[16];

--F1_b[18] is counter:inst6|b[18] at LC_X17_Y19_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[18] = DFFEAS(A1L102, GLOBAL(CLK27), VCC, , , F1L46, , , VCC);


--F1_b[13] is counter:inst6|b[13] at LC_X17_Y22_N2
--operation mode is normal

F1_b[13]_lut_out = F1L60;
F1_b[13] = DFFEAS(F1_b[13]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--F1_b[12] is counter:inst6|b[12] at LC_X17_Y20_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[12]_lut_out = GND;
F1_b[12] = DFFEAS(F1_b[12]_lut_out, GLOBAL(CLK27), VCC, , , F1L63, , , VCC);


--F1_b[11] is counter:inst6|b[11] at LC_X21_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[11]_lut_out = GND;
F1_b[11] = DFFEAS(F1_b[11]_lut_out, GLOBAL(CLK27), VCC, , , F1L65, , , VCC);


--A1L103 is rtl~461 at LC_X17_Y19_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[14]_qfbk = F1_b[14];
A1L103 = !F1_b[11] & !F1_b[12] & !F1_b[14]_qfbk & !F1_b[13];

--F1_b[14] is counter:inst6|b[14] at LC_X17_Y19_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[14] = DFFEAS(A1L103, GLOBAL(CLK27), VCC, , , F1L57, , , VCC);


--A1L104 is rtl~462 at LC_X17_Y19_N6
--operation mode is normal

A1L104 = A1L101 & A1L100 & A1L102 & A1L103;


--F1_b[9] is counter:inst6|b[9] at LC_X19_Y20_N5
--operation mode is normal

F1_b[9]_lut_out = F1L71;
F1_b[9] = DFFEAS(F1_b[9]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--F1_b[8] is counter:inst6|b[8] at LC_X19_Y20_N6
--operation mode is normal

F1_b[8]_lut_out = F1L74;
F1_b[8] = DFFEAS(F1_b[8]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--F1_b[7] is counter:inst6|b[7] at LC_X19_Y20_N2
--operation mode is normal

F1_b[7]_lut_out = F1L77;
F1_b[7] = DFFEAS(F1_b[7]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--A1L105 is rtl~463 at LC_X19_Y20_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[10]_qfbk = F1_b[10];
A1L105 = !F1_b[7] & !F1_b[8] & !F1_b[10]_qfbk & !F1_b[9];

--F1_b[10] is counter:inst6|b[10] at LC_X19_Y20_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[10] = DFFEAS(A1L105, GLOBAL(CLK27), VCC, , , F1L68, , , VCC);


--F1_b[6] is counter:inst6|b[6] at LC_X19_Y21_N9
--operation mode is normal

F1_b[6]_lut_out = F1L82;
F1_b[6] = DFFEAS(F1_b[6]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--F1_b[5] is counter:inst6|b[5] at LC_X18_Y23_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[5]_lut_out = GND;
F1_b[5] = DFFEAS(F1_b[5]_lut_out, GLOBAL(CLK27), VCC, , , F1L85, , , VCC);


--F1_b[4] is counter:inst6|b[4] at LC_X18_Y21_N0
--operation mode is normal

F1_b[4]_lut_out = F1L88;
F1_b[4] = DFFEAS(F1_b[4]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--A1L106 is rtl~464 at LC_X18_Y21_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[3]_qfbk = F1_b[3];
A1L106 = !F1_b[5] & !F1_b[6] & F1_b[3]_qfbk & !F1_b[4];

--F1_b[3] is counter:inst6|b[3] at LC_X18_Y21_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[3] = DFFEAS(A1L106, GLOBAL(CLK27), VCC, , , F1L79, , , VCC);


--F1_b[2] is counter:inst6|b[2] at LC_X17_Y21_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[2]_lut_out = GND;
F1_b[2] = DFFEAS(F1_b[2]_lut_out, GLOBAL(CLK27), VCC, , , F1L94, , , VCC);


--F1_b[0] is counter:inst6|b[0] at LC_X17_Y19_N8
--operation mode is normal

F1_b[0]_lut_out = !A1L98 & (F1L96);
F1_b[0] = DFFEAS(F1_b[0]_lut_out, GLOBAL(CLK27), VCC, , , , , , );


--A1L107 is rtl~465 at LC_X17_Y19_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[1]_qfbk = F1_b[1];
A1L107 = !F1_b[0] & (F1_b[1]_qfbk & !F1_b[2]);

--F1_b[1] is counter:inst6|b[1] at LC_X17_Y19_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_b[1] = DFFEAS(A1L107, GLOBAL(CLK27), VCC, , , F1L91, , , VCC);


--A1L98 is rtl~1 at LC_X17_Y19_N9
--operation mode is normal

A1L98 = A1L105 & A1L104 & A1L106 & A1L107;

--F1_HRRESET is counter:inst6|HRRESET at LC_X17_Y19_N9
--operation mode is normal

F1_HRRESET = DFFEAS(A1L98, GLOBAL(CLK27), VCC, , , , , , );


--E1_state.idle is sim_i2c:inst3|state.idle at LC_X12_Y8_N7
--operation mode is normal

E1_state.idle_lut_out = E1L118 # !E1_state.stop_c;
E1_state.idle = DFFEAS(E1_state.idle_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1_state.stop_c is sim_i2c:inst3|state.stop_c at LC_X12_Y8_N4
--operation mode is normal

E1_state.stop_c_lut_out = E1_state.stop_b # E1_state.stop_c & E1L118;
E1_state.stop_c = DFFEAS(E1_state.stop_c_lut_out, GLOBAL(F1_en), GLOBAL(F1_HRRESET), , , , , , );


--E1L25 is sim_i2c:inst3|add~387 at LC_X7_Y16_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_i[1]_qfbk = E1_i[1];
E1L25 = E1_i[0] & (E1_i[1]_qfbk);

--E1_i[1] is sim_i2c:inst3|i[1] at LC_X7_Y16_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_i[1] = DFFEAS(E1L25, GLOBAL(E1_WrDone), VCC, , , E1L29, , , VCC);


--E1L26 is sim_i2c:inst3|add~388 at LC_X7_Y16_N1
--operation mode is normal

E1_i[4]_qfbk = E1_i[4];
E1L26 = E1_i[4]_qfbk $ (E1_i[2] & E1_i[3] & E1L25);

--E1_i[4] is sim_i2c:inst3|i[4] at LC_X7_Y16_N1
--operation mode is normal

E1_i[4] = DFFEAS(E1L26, GLOBAL(E1_WrDone), VCC, , , , , , );


--E1L27 is sim_i2c:inst3|add~389 at LC_X9_Y8_N2
--operation mode is normal

E1_i[3]_qfbk = E1_i[3];
E1L27 = E1_i[3]_qfbk $ (E1_i[1] & E1_i[2] & E1_i[0]);

--E1_i[3] is sim_i2c:inst3|i[3] at LC_X9_Y8_N2
--operation mode is normal

E1_i[3] = DFFEAS(E1L27, GLOBAL(E1_WrDone), VCC, , , , , , );


--E1L28 is sim_i2c:inst3|add~390 at LC_X7_Y16_N2
--operation mode is normal

E1_i[2]_qfbk = E1_i[2];
E1L28 = E1_i[2]_qfbk $ (E1_i[0] & E1_i[1]);

--E1_i[2] is sim_i2c:inst3|i[2] at LC_X7_Y16_N2
--operation mode is normal

E1_i[2] = DFFEAS(E1L28, GLOBAL(E1_WrDone), VCC, , , , , , );


--E1L29 is sim_i2c:inst3|add~391 at LC_X9_Y8_N4
--operation mode is normal

E1L29 = E1_i[1] $ E1_i[0];


--G1L9Q is sld_hub:sld_hub_inst|hub_tdo~385 at LC_X7_Y22_N0
--operation mode is normal

G1L9Q = AMPP_FUNCTION(A1L7, LB1_state[4], LB1_state[3], G1_jtag_debug_mode_usr1, JB6_Q[0], !LB1_state[8]);


--G1L10Q is sld_hub:sld_hub_inst|hub_tdo~386 at LC_X7_Y22_N1
--operation mode is normal

G1L10Q = AMPP_FUNCTION(A1L7, G1L13, G1L12, P4_dffs[0], JB4_Q[4], !LB1_state[8]);


--G1L7Q is sld_hub:sld_hub_inst|hub_tdo~383 at LC_X7_Y22_N9
--operation mode is normal

G1L7Q = AMPP_FUNCTION(A1L7, G1L14, JB7_Q[0], G1_jtag_debug_mode_usr1, LB1L18, !LB1_state[8]);


--G1L8Q is sld_hub:sld_hub_inst|hub_tdo~384 at LC_X7_Y22_N8
--operation mode is normal

G1L8Q = AMPP_FUNCTION(A1L7, JB3_Q[0], G1L11, G1_jtag_debug_mode_usr1, LB1L18, !LB1_state[8]);


--G1L11 is sld_hub:sld_hub_inst|hub_tdo~455 at LC_X7_Y22_N5
--operation mode is normal

G1L11 = AMPP_FUNCTION(G1L8Q, G1L7Q, G1L10Q, G1L9Q);


--F1L8 is counter:inst6|add~497 at LC_X1_Y14_N1
--operation mode is arithmetic

F1L8 = !F1_a[0];

--F1L9 is counter:inst6|add~499 at LC_X1_Y14_N1
--operation mode is arithmetic

F1L9_cout_0 = F1_a[0];
F1L9 = CARRY(F1L9_cout_0);

--F1L10 is counter:inst6|add~499COUT1_663 at LC_X1_Y14_N1
--operation mode is arithmetic

F1L10_cout_1 = F1_a[0];
F1L10 = CARRY(F1L10_cout_1);


--F1L11 is counter:inst6|add~502 at LC_X1_Y14_N6
--operation mode is normal

F1L11_carry_eqn = (!F1L16 & F1L13) # (F1L16 & F1L14);
F1L11 = F1L11_carry_eqn $ F1_a[5];


--F1L12 is counter:inst6|add~507 at LC_X1_Y14_N5
--operation mode is arithmetic

F1L12_carry_eqn = (!F1L16 & GND) # (F1L16 & VCC);
F1L12 = F1_a[4] $ !F1L12_carry_eqn;

--F1L13 is counter:inst6|add~509 at LC_X1_Y14_N5
--operation mode is arithmetic

F1L13_cout_0 = F1_a[4] & !F1L16;
F1L13 = CARRY(F1L13_cout_0);

--F1L14 is counter:inst6|add~509COUT1_665 at LC_X1_Y14_N5
--operation mode is arithmetic

F1L14_cout_1 = F1_a[4] & !F1L16;
F1L14 = CARRY(F1L14_cout_1);


--F1L15 is counter:inst6|add~512 at LC_X1_Y14_N4
--operation mode is arithmetic

F1L15 = F1_a[3] $ (F1L20);

--F1L16 is counter:inst6|add~514 at LC_X1_Y14_N4
--operation mode is arithmetic

F1L16 = F1L17;


--F1L19 is counter:inst6|add~517 at LC_X1_Y14_N3
--operation mode is arithmetic

F1L19 = F1_a[2] $ !F1L23;