v_fpga.map.rpt

自己写的iic配置芯片的源程序

; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Stratix/Stratix GX                       ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto DSP Block Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                  ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K/M9K Memory Blocks                            ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM/M144K Memory Blocks                        ; Unlimited          ; Unlimited          ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                   ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                   ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------------------+
; v_transfer2.vhd                  ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer2.vhd       ;
; v_fpga.bdf                       ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_fpga.bdf            ;
; v_transfer.vhd                   ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/v_transfer.vhd        ;
; Init9011.vhd                     ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/i2c备份/writeI2C_seq_suc5.9/Init9011.vhd          ;