v_fpga.map.rpt

自己写的iic配置芯片的源程序

Analysis & Synthesis report for v_fpga
Tue May 20 16:42:15 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |v_fpga|Init9011:inst1|state
  9. User-Specified and Inferred Latches
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Gate-level Retiming
 14. Source assignments for Init9011:inst1|altsyncram:Mux0_rtl_0|altsyncram_ibu:auto_generated
 15. Parameter Settings for Inferred Entity Instance: Init9011:inst1|altsyncram:Mux0_rtl_0
 16. Analysis & Synthesis Messages



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; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



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