toubiyinliao.txt

verilog HDL自动投币售饮料机程序

module yy(in,rst,clk,out,xian,cs);
input rst,clk;
input [2:0] in;
output [7:0] xian;
output out;
output [3:0] cs;
reg     [3:0] cs;
reg    [25:0] count;
reg    [2:0]  state;
reg    [7:0] xian;
reg           out;
reg           clk1;
always @(posedge clk)
begin     count=count+1;
      if(count==50000000) 
begin      count=0;  
        clk1=~clk1;   
    end
end 
always @(posedge clk1)
begin 
cs=4'b1110;     
  if(!rst)  
begin   state='b000; 
          out=1;  
         xian='b111_1110; 
end  
   else 
     begin       
    case(state)
       'b000:begin    
                 if(in=='b110)  
                       begin      
                           state='b001; 
                            out=1;  
                            xian='b000_0110; 
                        end 
                  if(in=='b101) 
                         begin  
                            state='b010; 
                            out=1; 
                            xian='b101_1011; 
                        end 
                   if(in=='b011) 
                          begin  
                             state='b000; 
                             out=0; 
                             xian='b110_1101; 
                          end     
                   end
              'b001:begin 
                  if(in=='b110) 
                         begin  
                             state='b010; 
                             out=1;
                             xian='b101_1011;
                        end 
                  if(in=='b101) 
                          begin   
                             state='b011; 
                             out=1; 
                             xian='b100_1111; 
                           end
                   if(in=='b011) 
                         begin     
                              state='b001;
                              out=0; 
                               xian='b000_0110; 
                         end     
                     end 
                  'b010:
                     begin 
                       if(in=='b110)
                           begin     
                               state='b011; 
                               out=1; 
                              xian='b000_0110; 
                           end  
                       if(in=='b101) 
                           begin    
                              state='b100;  
                              out=1;
                             xian='b110_0110; 
                          end
                       if(in=='b011) 
                           begin   
                             state='b010;   
                             out=0; 
                             xian='b1011_011; 
                          end    
                      end  
                   'b011:
                      begin     
                          if(in=='b110)  
                              begin   
                                 state='b100;  
                                 out=1; 
                                 xian='b110_0110; 
                              end  
                           if(in=='b101) 
                               begin   
                                    state='b000;
                                    out=0;  
                                    xian='b110_1101; 
                                 end 
                            if(in=='b011)
                                  begin     
                                     state='b011;  
                                     out=0; 
                                     xian='b101_1011;  
                                  end   
                          end  
                     'b100:
                         begin    
                             if(in=='b110) 
                                   begin      
                                      state='b000; 
                                      out=0; 
                                      xian='b011_1111;
                                   end  
                               if(in=='b101)
                                    begin  
                                      state='b001;
                                      out=0; 
                                      xian='b000_0110; 
                                   end
                               if(in=='b011)  
                                   begin   
                                      state='b100;
                                     out=0; 
                                    xian='b110_0110; 
                                  end   
                             end 
                        endcase  
   end
end

endmodule