vga_key_map.mrp

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

Release 8.2.03i Map I.34
Xilinx Mapping Report File for Design 'vga_key'

Design Information
------------------
Command Line   : F:\Xilinx\bin\nt\map.exe -ise
F:/basys/basys/huanyizuoyi17/huanyizuoyi/VGAVGA/VGAVGA.ise -intstyle ise -p
xc3s100e-tq144-4 -cm area -pr b -k 4 -c 100 -o vga_key_map.ncd vga_key.ngd
vga_key.pcf 
Target Device  : xc3s100e
Target Package : tq144
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.34.32.1 $
Mapped Date    : Sat May 03 16:12:20 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         259 out of   1,920   13%
  Number of 4 input LUTs:             554 out of   1,920   28%
Logic Distribution:
  Number of occupied Slices:                          378 out of     960   39%
    Number of Slices containing only related logic:     378 out of     378  100%
    Number of Slices containing unrelated logic:          0 out of     378    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            681 out of   1,920   35%
  Number used as logic:                554
  Number used as a route-thru:         127
  Number of bonded IOBs:               28 out of     108   25%
  Number of Block RAMs:                2 out of       4   50%
  Number of GCLKs:                     2 out of      24    8%

Total equivalent gate count for design:  137,657
Additional JTAG gate count for IOBs:  1,344
Peak Memory Usage:  158 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network m1/m3/douta<0> has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
   more times for the following (max. 5 shown):
   m1/m3/BU2/N6
   To see the details of these warning messages, please use the -detail switch.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_ibuf" (output signal=clk_c),
   BUFG symbol "m2/m1/count16_inferred_clock_cb[14]" (output signal=m2/clkout)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   6 block(s) removed
  10 block(s) optimized away
   7 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "m1/m3/douta<0>" is sourceless and has been removed.
The signal "m1/m3/BU2/U0/blk_mem_generator/valid.cstr/has_mux_b.B/_xor0001" is
sourceless and has been removed.
The signal "m1/m3/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/_xor0001" is
sourceless and has been removed.
 Sourceless block
"m1/m3/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0" (FF) removed.
  The signal "m1/m3/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>"
is sourceless and has been removed.
   Sourceless block
"m1/m3/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/_mux00001" (ROM) removed.
The signal "m1/m3/BU2/U0/blk_mem_generator/valid.cstr/ram_douta" is sourceless
and has been removed.
The signal "m1/m3/BU2/U0/blk_mem_generator/valid.cstr/ram_douta0" is sourceless
and has been removed.
The signal "m1/m3/BU2/N6" is sourceless and has been removed.
Unused block "m1/m3/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/_xor00011"
(ROM) removed.
Unused block "m1/m3/BU2/XST_VCC" (ONE) removed.
Unused block "m1/m3/GND" (ZERO) removed.
Unused block "m1/m3/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		m1/GND
GND 		m1/m1/GND
GND 		m1/m2/GND
VCC 		m1/m2/VCC
INV 		m1/m3/BU2/U0/blk_mem_generator/valid.cstr/has_mux_b.B/_xor00011_INV_0
GND 		m1/m3/BU2/XST_GND
GND 		m1/m4/GND
VCC 		m1/m4/VCC
GND 		m2/m1/GND
GND 		m2/m2/GND

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+-----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | IOB Type         | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IBUF/IFD  |
|                                    |                  |           |             | Strength | Rate |              |          | Delay     |
+-----------------------------------------------------------------------------------------------------------------------------------------+
| blue[0]                            | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| blue[1]                            | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| button[0]                          | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| button[1]                          | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| button[2]                          | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| button[3]                          | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| clk                                | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| ea[0]                              | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| ea[1]                              | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| ea[2]                              | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| ea[3]                              | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| green[0]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| green[1]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| green[2]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| hs                                 | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| red[0]                             | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| red[1]                             | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| red[2]                             | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| rst                                | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| seven[0]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| seven[1]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| seven[2]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| seven[3]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| seven[4]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| seven[5]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| seven[6]                           | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
| sw2                                | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| vs                                 | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
+-----------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings