savecon1.v

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:17:39 11/11/2007 
// Design Name: 
// Module Name:    savecon 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module savecon(clk, rst,date,sw3, counths, countvs, red, green, blue,  addre2,web);
    input clk;
    input rst;
	 input date;
	 input sw3;
    input [9:0] counths;
    input [9:0] countvs;
    output [2:0] red;
    output [2:0] green;
    output [1:0] blue;
//   output [14:0] addre1;
    output [14:0] addre2;
	 output web;
	 wire web;
	 reg  [2:0] red;
	 reg  [2:0] green;
	 reg  [1:0] blue;
    reg  [14:0] addre1;
	 reg  [14:0] addre2;
	 reg dateb;
	 reg [7:0] m;
	 reg [14:0] z;
	 reg [7:0] count160;

assign web=0;
	 
always@( posedge clk or negedge rst)
 begin
   if(!rst)  
	 addre2<=19199;
	else
	 begin
	  if(countvs>181 &&countvs<302)  //qian bian 2 ge di dian ping
	    begin
		   if(counths>383 && counths<544) //qian bian 144 ge di dianping
			  begin
			    if(addre2==19199)
				   addre2<=0;
				 else
				   begin
					dateb<=1;
				   addre2<=addre2+1;
					end
			  end
			 else
			   dateb<=0;
		 end
		else
		 dateb<=0;
	 end
 end
 
always@( posedge clk or negedge rst)
 begin
   if(!rst) 
     begin
	    red<=0;
		 green<=0;
		 blue<=0;
     end	  
	else
	  begin
	   if(counths<97)
		   begin
	       red<=0;
		    green<=0;
		    blue<=0;
         end
	    else if(date==1 && dateb==1)
		   begin
	       red<=7;
		    green<=0;
		    blue<=0;
         end	
		 else
		    begin
	       red<=0;
		    green<=0;
		    blue<=3;
         end	
	  end
 end

endmodule