coregen.xml

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· XML 代码 · 共 73 行

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="save" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
save YourInstanceName (
    .clka(clka),
    .dina(dina),
    .addra(addra),
    .wea(wea),
    .ssra(ssra),
    .douta(douta),
    .clkb(clkb),
    .dinb(dinb),
    .addrb(addrb),
    .web(web),
    .doutb(doutb));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="save" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component save
    port (
    clka: IN std_logic;
    dina: IN std_logic_VECTOR(0 downto 0);
    addra: IN std_logic_VECTOR(14 downto 0);
    wea: IN std_logic_VECTOR(0 downto 0);
    ssra: IN std_logic;
    douta: OUT std_logic_VECTOR(0 downto 0);
    clkb: IN std_logic;
    dinb: IN std_logic_VECTOR(0 downto 0);
    addrb: IN std_logic_VECTOR(14 downto 0);
    web: IN std_logic_VECTOR(0 downto 0);
    doutb: OUT std_logic_VECTOR(0 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : save
        port map (
            clka =&gt; clka,
            dina =&gt; dina,
            addra =&gt; addra,
            wea =&gt; wea,
            ssra =&gt; ssra,
            douta =&gt; douta,
            clkb =&gt; clkb,
            dinb =&gt; dinb,
            addrb =&gt; addrb,
            web =&gt; web,
            doutb =&gt; doutb);
 
		</Template>
	</Folder>
</RootFolder>