vga_key.ncf

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
NET "clk" TNM_NET = "clk"; 
TIMESPEC "TS_clk" = PERIOD "clk" 9.502 ns HIGH 50.00%; 
NET "m2/m1/clkout_c" TNM_NET = "m2_m1_clkout_c"; 
TIMESPEC "TS_m2_m1_clkout_c" = PERIOD "m2_m1_clkout_c" 4.148 ns HIGH 50.00%; 
#End clock constraints

# Output Constraints
# Input Constraints

# I/O Registers Packing Constraints
INST "m2/m3/seven[6]" IOB=FALSE;
INST "m2/m3/seven[5]" IOB=FALSE;
INST "m2/m3/seven[4]" IOB=FALSE;
INST "m2/m3/seven[3]" IOB=FALSE;
INST "m2/m3/seven[2]" IOB=FALSE;
INST "m2/m3/seven[1]" IOB=FALSE;
INST "m2/m3/seven[0]" IOB=FALSE;
INST "m1/m2/red[0]" IOB=FALSE;
INST "m1/m2/blue[1]" IOB=FALSE;
INST "m1/m2/blue[0]" IOB=FALSE;
INST "m1/m2/green[2]" IOB=FALSE;
INST "m1/m2/green[1]" IOB=FALSE;
INST "m1/m2/green[0]" IOB=FALSE;
INST "m1/m2/red[2]" IOB=FALSE;
INST "m1/m2/red[1]" IOB=FALSE;
INST "m1/m1/vs" IOB=FALSE;
INST "m1/m1/hs" IOB=FALSE;

# Location Constraints

# End of generated constraints