vga.vif

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  vga.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Xilinx

# RTL and technology files
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original -verilog ../../../../Synplicity/fpga_81/bin/../lib/xilinx/unisim.v
vif_add_file -original -verilog ./vs_hs.v
vif_add_file -original -verilog ./sendsave.v
vif_add_file -original -verilog ./savecon.v
vif_add_file -original -verilog ./save.v
vif_add_file -original -verilog ./vga.v
vif_set_top_module -original -top vga
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog vga.vm
vif_set_top_module -translated -top vga 
# Read FSM encoding

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies

# Technology sequential redundancies
vif_set_equiv -translated m1/countvs_Z[4] m1/countvs_fast_Z[4]
vif_set_equiv -translated m1/countvs_Z[5] m1/countvs_fast_Z[5]
vif_set_equiv -translated m2/z_Z[5] m2/z_fast_Z[5]

# Inversion map points

# Port mappping and directions

# Black box mapping
vif_set_black_box save

vif_set_map_point -blackbox -original m3 -translated m3

# Other sequential cells, including multidimensional arrays
vif_set_map_point -register -original m2/red[0] -translated m2/red_1_Z[0]
vif_set_map_point -register -original m2/blue[0] -translated m2/blue_1_Z[0]

# Constant Registers

# Retimed Registers